cxl/core/cdat.c

599  * doing walking the port hierarchy to deal with shared upstream link.
611  *          indexed by the upstream device with data of 'struct cxl_perf_ctx'.
617  * an xarray indexed by the upstream device of the switch or the RP
619  * from the endpoint CDAT, the endpoint upstream link bandwidth, and the
620  * bandwidth from the SSLBIS of the switch CDAT for the switch upstream port to
659 	 * otherwise it's the parent switch upstream device.  in cxl_endpoint_gather_bandwidth()
680 	/* Direct upstream link from EP bandwidth */  in cxl_endpoint_gather_bandwidth()
686 	 * Min of upstream link bandwidth and Endpoint CDAT bandwidth from  in cxl_endpoint_gather_bandwidth()
713 	 * of the endpoints with the same switch upstream device or RP.  in cxl_endpoint_gather_bandwidth()
738  * @input_xa: xarray indexed by upstream device of a switch with data of 'struct  in DEFINE_FREE()
746  * bandwidth, the upstream link bandwidth, and the SSLBIS of the upstream  in DEFINE_FREE()
747  * switch if exists. Sum the resulting bandwidth under the switch upstream  in DEFINE_FREE()
785 		 * otherwise it's the parent switch upstream device.  in DEFINE_FREE()
808 		 * If the device isn't an upstream PCIe port, there's something  in DEFINE_FREE()
814 		/* Retrieve the upstream link bandwidth */  in DEFINE_FREE()
820 		 * Take the min of downstream bandwidth and the upstream link  in DEFINE_FREE()
826 		 * Take the min of the calculated bandwdith and the upstream  in DEFINE_FREE()
833 		 * Aggregate the calculated bandwidth common to an upstream  in DEFINE_FREE()