Lines Matching refs:chip_info
304 unsigned int reset_mask = handle->chip_info->icp_rst_mask; in qat_hal_reset()
305 unsigned int reset_csr = handle->chip_info->icp_rst_csr; in qat_hal_reset()
423 misc_ctl_csr = handle->chip_info->misc_ctl_csr; in qat_hal_reset_timestamp()
475 unsigned int clk_csr = handle->chip_info->glb_clk_enable_csr; in qat_hal_clr_reset()
476 unsigned int reset_mask = handle->chip_info->icp_rst_mask; in qat_hal_clr_reset()
477 unsigned int reset_csr = handle->chip_info->icp_rst_csr; in qat_hal_clr_reset()
637 if (handle->chip_info->nn) in qat_hal_clear_gpr()
701 handle->chip_info->mmp_sram_size = 0; in qat_hal_chip_init()
702 handle->chip_info->nn = false; in qat_hal_chip_init()
703 handle->chip_info->lm2lm3 = true; in qat_hal_chip_init()
704 handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG_2X; in qat_hal_chip_init()
705 handle->chip_info->icp_rst_csr = ICP_RESET_CPP0; in qat_hal_chip_init()
707 handle->chip_info->icp_rst_mask = 0x100155; in qat_hal_chip_init()
709 handle->chip_info->icp_rst_mask = 0x100015; in qat_hal_chip_init()
710 handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE_CPP0; in qat_hal_chip_init()
711 handle->chip_info->misc_ctl_csr = MISC_CONTROL_C4XXX; in qat_hal_chip_init()
712 handle->chip_info->wakeup_event_val = 0x80000000; in qat_hal_chip_init()
713 handle->chip_info->fw_auth = true; in qat_hal_chip_init()
714 handle->chip_info->css_3k = true; in qat_hal_chip_init()
715 handle->chip_info->tgroup_share_ustore = true; in qat_hal_chip_init()
716 handle->chip_info->fcu_ctl_csr = FCU_CONTROL_4XXX; in qat_hal_chip_init()
717 handle->chip_info->fcu_sts_csr = FCU_STATUS_4XXX; in qat_hal_chip_init()
718 handle->chip_info->fcu_dram_addr_hi = FCU_DRAM_ADDR_HI_4XXX; in qat_hal_chip_init()
719 handle->chip_info->fcu_dram_addr_lo = FCU_DRAM_ADDR_LO_4XXX; in qat_hal_chip_init()
720 handle->chip_info->fcu_loaded_ae_csr = FCU_AE_LOADED_4XXX; in qat_hal_chip_init()
721 handle->chip_info->fcu_loaded_ae_pos = 0; in qat_hal_chip_init()
732 handle->chip_info->mmp_sram_size = 0; in qat_hal_chip_init()
733 handle->chip_info->nn = true; in qat_hal_chip_init()
734 handle->chip_info->lm2lm3 = false; in qat_hal_chip_init()
735 handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG; in qat_hal_chip_init()
736 handle->chip_info->icp_rst_csr = ICP_RESET; in qat_hal_chip_init()
737 handle->chip_info->icp_rst_mask = (hw_data->ae_mask << RST_CSR_AE_LSB) | in qat_hal_chip_init()
739 handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE; in qat_hal_chip_init()
740 handle->chip_info->misc_ctl_csr = MISC_CONTROL; in qat_hal_chip_init()
741 handle->chip_info->wakeup_event_val = WAKEUP_EVENT; in qat_hal_chip_init()
742 handle->chip_info->fw_auth = true; in qat_hal_chip_init()
743 handle->chip_info->css_3k = false; in qat_hal_chip_init()
744 handle->chip_info->tgroup_share_ustore = false; in qat_hal_chip_init()
745 handle->chip_info->fcu_ctl_csr = FCU_CONTROL; in qat_hal_chip_init()
746 handle->chip_info->fcu_sts_csr = FCU_STATUS; in qat_hal_chip_init()
747 handle->chip_info->fcu_dram_addr_hi = FCU_DRAM_ADDR_HI; in qat_hal_chip_init()
748 handle->chip_info->fcu_dram_addr_lo = FCU_DRAM_ADDR_LO; in qat_hal_chip_init()
749 handle->chip_info->fcu_loaded_ae_csr = FCU_STATUS; in qat_hal_chip_init()
750 handle->chip_info->fcu_loaded_ae_pos = FCU_LOADED_AE_POS; in qat_hal_chip_init()
759 handle->chip_info->mmp_sram_size = 0x40000; in qat_hal_chip_init()
760 handle->chip_info->nn = true; in qat_hal_chip_init()
761 handle->chip_info->lm2lm3 = false; in qat_hal_chip_init()
762 handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG; in qat_hal_chip_init()
763 handle->chip_info->icp_rst_csr = ICP_RESET; in qat_hal_chip_init()
764 handle->chip_info->icp_rst_mask = (hw_data->ae_mask << RST_CSR_AE_LSB) | in qat_hal_chip_init()
766 handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE; in qat_hal_chip_init()
767 handle->chip_info->misc_ctl_csr = MISC_CONTROL; in qat_hal_chip_init()
768 handle->chip_info->wakeup_event_val = WAKEUP_EVENT; in qat_hal_chip_init()
769 handle->chip_info->fw_auth = false; in qat_hal_chip_init()
770 handle->chip_info->css_3k = false; in qat_hal_chip_init()
771 handle->chip_info->tgroup_share_ustore = false; in qat_hal_chip_init()
772 handle->chip_info->fcu_ctl_csr = 0; in qat_hal_chip_init()
773 handle->chip_info->fcu_sts_csr = 0; in qat_hal_chip_init()
774 handle->chip_info->fcu_dram_addr_hi = 0; in qat_hal_chip_init()
775 handle->chip_info->fcu_dram_addr_lo = 0; in qat_hal_chip_init()
776 handle->chip_info->fcu_loaded_ae_csr = 0; in qat_hal_chip_init()
777 handle->chip_info->fcu_loaded_ae_pos = 0; in qat_hal_chip_init()
790 if (handle->chip_info->mmp_sram_size > 0) { in qat_hal_chip_init()
842 handle->chip_info = kzalloc(sizeof(*handle->chip_info), GFP_KERNEL); in qat_hal_init()
843 if (!handle->chip_info) { in qat_hal_init()
862 if (!handle->chip_info->fw_auth) { in qat_hal_init()
872 kfree(handle->chip_info); in qat_hal_init()
884 kfree(handle->chip_info); in qat_hal_deinit()
892 u32 wakeup_val = handle->chip_info->wakeup_event_val; in qat_hal_start()
899 if (handle->chip_info->fw_auth) { in qat_hal_start()
900 fcu_ctl_csr = handle->chip_info->fcu_ctl_csr; in qat_hal_start()
901 fcu_sts_csr = handle->chip_info->fcu_sts_csr; in qat_hal_start()
925 if (!handle->chip_info->fw_auth) in qat_hal_stop()
1016 if (handle->chip_info->lm2lm3) { in qat_hal_exec_micro_inst()
1087 if (handle->chip_info->lm2lm3) { in qat_hal_exec_micro_inst()
1578 if (!handle->chip_info->nn) { in qat_hal_init_nn()