Lines Matching refs:qm
311 struct hisi_qm *qm = s->private; in sec_diff_regs_show() local
313 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, in sec_diff_regs_show()
399 u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low) in sec_get_alg_bitmap() argument
403 cap_val_h = qm->cap_tables.dev_cap_table[high].cap_val; in sec_get_alg_bitmap()
404 cap_val_l = qm->cap_tables.dev_cap_table[low].cap_val; in sec_get_alg_bitmap()
429 static void sec_set_endian(struct hisi_qm *qm) in sec_set_endian() argument
433 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
441 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
444 static void sec_engine_sva_config(struct hisi_qm *qm) in sec_engine_sva_config() argument
448 if (qm->ver > QM_HW_V2) { in sec_engine_sva_config()
449 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
452 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
455 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
459 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
462 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
465 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
467 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
470 if (qm->use_sva) in sec_engine_sva_config()
474 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
479 static void sec_open_sva_prefetch(struct hisi_qm *qm) in sec_open_sva_prefetch() argument
484 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) in sec_open_sva_prefetch()
488 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); in sec_open_sva_prefetch()
490 writel(val, qm->io_base + SEC_PREFETCH_CFG); in sec_open_sva_prefetch()
492 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG, in sec_open_sva_prefetch()
496 pci_err(qm->pdev, "failed to open sva prefetch\n"); in sec_open_sva_prefetch()
499 static void sec_close_sva_prefetch(struct hisi_qm *qm) in sec_close_sva_prefetch() argument
504 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) in sec_close_sva_prefetch()
507 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); in sec_close_sva_prefetch()
509 writel(val, qm->io_base + SEC_PREFETCH_CFG); in sec_close_sva_prefetch()
511 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_SVA_TRANS, in sec_close_sva_prefetch()
515 pci_err(qm->pdev, "failed to close sva prefetch\n"); in sec_close_sva_prefetch()
518 static void sec_enable_clock_gate(struct hisi_qm *qm) in sec_enable_clock_gate() argument
522 if (qm->ver < QM_HW_V3) in sec_enable_clock_gate()
525 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()
527 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()
529 val = readl(qm->io_base + SEC_DYNAMIC_GATE_REG); in sec_enable_clock_gate()
531 writel(val, qm->io_base + SEC_DYNAMIC_GATE_REG); in sec_enable_clock_gate()
533 val = readl(qm->io_base + SEC_CORE_AUTO_GATE); in sec_enable_clock_gate()
535 writel(val, qm->io_base + SEC_CORE_AUTO_GATE); in sec_enable_clock_gate()
538 static void sec_disable_clock_gate(struct hisi_qm *qm) in sec_disable_clock_gate() argument
543 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()
545 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()
548 static int sec_engine_init(struct hisi_qm *qm) in sec_engine_init() argument
554 sec_disable_clock_gate(qm); in sec_engine_init()
556 writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG); in sec_engine_init()
558 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_MEM_INIT_DONE_REG, in sec_engine_init()
562 pci_err(qm->pdev, "fail to init sec mem\n"); in sec_engine_init()
566 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_engine_init()
568 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_engine_init()
570 sec_engine_sva_config(qm); in sec_engine_init()
573 qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS); in sec_engine_init()
575 reg = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CORE_ENABLE_BITMAP, qm->cap_ver); in sec_engine_init()
576 writel(reg, qm->io_base + SEC_SAA_EN_REG); in sec_engine_init()
578 if (qm->ver < QM_HW_V3) { in sec_engine_init()
581 qm->io_base + SEC_BD_ERR_CHK_EN_REG0); in sec_engine_init()
585 qm->io_base + SEC_BD_ERR_CHK_EN_REG1); in sec_engine_init()
587 qm->io_base + SEC_BD_ERR_CHK_EN_REG3); in sec_engine_init()
591 sec_set_endian(qm); in sec_engine_init()
593 sec_enable_clock_gate(qm); in sec_engine_init()
598 static int sec_set_user_domain_and_cache(struct hisi_qm *qm) in sec_set_user_domain_and_cache() argument
601 writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1); in sec_set_user_domain_and_cache()
602 writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
603 writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1); in sec_set_user_domain_and_cache()
604 writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
605 writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
608 writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG); in sec_set_user_domain_and_cache()
609 writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
612 writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG); in sec_set_user_domain_and_cache()
613 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE); in sec_set_user_domain_and_cache()
618 FIELD_PREP(CQC_CACHE_WB_THRD, 1), qm->io_base + QM_CACHE_CTL); in sec_set_user_domain_and_cache()
620 return sec_engine_init(qm); in sec_set_user_domain_and_cache()
624 static void sec_debug_regs_clear(struct hisi_qm *qm) in sec_debug_regs_clear() argument
629 writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE); in sec_debug_regs_clear()
631 readl(qm->io_base + sec_dfx_regs[i].offset); in sec_debug_regs_clear()
634 writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE); in sec_debug_regs_clear()
636 hisi_qm_debug_regs_clear(qm); in sec_debug_regs_clear()
639 static void sec_master_ooo_ctrl(struct hisi_qm *qm, bool enable) in sec_master_ooo_ctrl() argument
643 val1 = readl(qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()
646 val2 = hisi_qm_get_hw_info(qm, sec_basic_info, in sec_master_ooo_ctrl()
647 SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); in sec_master_ooo_ctrl()
653 if (qm->ver > QM_HW_V2) in sec_master_ooo_ctrl()
654 writel(val2, qm->io_base + SEC_OOO_SHUTDOWN_SEL); in sec_master_ooo_ctrl()
656 writel(val1, qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()
659 static void sec_hw_error_enable(struct hisi_qm *qm) in sec_hw_error_enable() argument
663 if (qm->ver == QM_HW_V1) { in sec_hw_error_enable()
664 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); in sec_hw_error_enable()
665 pci_info(qm->pdev, "V1 not support hw error handle\n"); in sec_hw_error_enable()
669 ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CE_MASK_CAP, qm->cap_ver); in sec_hw_error_enable()
670 nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver); in sec_hw_error_enable()
673 writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_SOURCE); in sec_hw_error_enable()
676 writel(ce, qm->io_base + SEC_RAS_CE_REG); in sec_hw_error_enable()
677 writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG); in sec_hw_error_enable()
678 writel(nfe, qm->io_base + SEC_RAS_NFE_REG); in sec_hw_error_enable()
681 sec_master_ooo_ctrl(qm, true); in sec_hw_error_enable()
684 writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_MASK); in sec_hw_error_enable()
687 static void sec_hw_error_disable(struct hisi_qm *qm) in sec_hw_error_disable() argument
690 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); in sec_hw_error_disable()
693 sec_master_ooo_ctrl(qm, false); in sec_hw_error_disable()
696 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG); in sec_hw_error_disable()
697 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG); in sec_hw_error_disable()
698 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG); in sec_hw_error_disable()
701 static u32 sec_clear_enable_read(struct hisi_qm *qm) in sec_clear_enable_read() argument
703 return readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) & in sec_clear_enable_read()
707 static int sec_clear_enable_write(struct hisi_qm *qm, u32 val) in sec_clear_enable_write() argument
714 tmp = (readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) & in sec_clear_enable_write()
716 writel(tmp, qm->io_base + SEC_CTRL_CNT_CLR_CE); in sec_clear_enable_write()
726 struct hisi_qm *qm = file->qm; in sec_debug_read() local
730 ret = hisi_qm_get_dfx_access(qm); in sec_debug_read()
738 val = sec_clear_enable_read(qm); in sec_debug_read()
746 hisi_qm_put_dfx_access(qm); in sec_debug_read()
752 hisi_qm_put_dfx_access(qm); in sec_debug_read()
761 struct hisi_qm *qm = file->qm; in sec_debug_write() local
780 ret = hisi_qm_get_dfx_access(qm); in sec_debug_write()
788 ret = sec_clear_enable_write(qm, val); in sec_debug_write()
801 hisi_qm_put_dfx_access(qm); in sec_debug_write()
841 static int sec_core_debug_init(struct hisi_qm *qm) in sec_core_debug_init() argument
843 struct dfx_diff_registers *sec_regs = qm->debug.acc_diff_regs; in sec_core_debug_init()
844 struct sec_dev *sec = container_of(qm, struct sec_dev, qm); in sec_core_debug_init()
845 struct device *dev = &qm->pdev->dev; in sec_core_debug_init()
851 tmp_d = debugfs_create_dir("sec_dfx", qm->debug.debug_root); in sec_core_debug_init()
859 regset->base = qm->io_base; in sec_core_debug_init()
862 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) in sec_core_debug_init()
864 if (qm->fun_type == QM_HW_PF && sec_regs) in sec_core_debug_init()
866 qm, &sec_diff_regs_fops); in sec_core_debug_init()
878 static int sec_debug_init(struct hisi_qm *qm) in sec_debug_init() argument
880 struct sec_dev *sec = container_of(qm, struct sec_dev, qm); in sec_debug_init()
883 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) { in sec_debug_init()
887 sec->debug.files[i].qm = qm; in sec_debug_init()
890 qm->debug.debug_root, in sec_debug_init()
896 return sec_core_debug_init(qm); in sec_debug_init()
899 static int sec_debugfs_init(struct hisi_qm *qm) in sec_debugfs_init() argument
901 struct device *dev = &qm->pdev->dev; in sec_debugfs_init()
904 ret = hisi_qm_regs_debugfs_init(qm, sec_diff_regs, ARRAY_SIZE(sec_diff_regs)); in sec_debugfs_init()
910 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), in sec_debugfs_init()
912 qm->debug.sqe_mask_offset = SEC_SQE_MASK_OFFSET; in sec_debugfs_init()
913 qm->debug.sqe_mask_len = SEC_SQE_MASK_LEN; in sec_debugfs_init()
915 hisi_qm_debug_init(qm); in sec_debugfs_init()
917 ret = sec_debug_init(qm); in sec_debugfs_init()
924 debugfs_remove_recursive(qm->debug.debug_root); in sec_debugfs_init()
925 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(sec_diff_regs)); in sec_debugfs_init()
929 static void sec_debugfs_exit(struct hisi_qm *qm) in sec_debugfs_exit() argument
931 debugfs_remove_recursive(qm->debug.debug_root); in sec_debugfs_exit()
933 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(sec_diff_regs)); in sec_debugfs_exit()
936 static int sec_show_last_regs_init(struct hisi_qm *qm) in sec_show_last_regs_init() argument
938 struct qm_debug *debug = &qm->debug; in sec_show_last_regs_init()
947 debug->last_words[i] = readl_relaxed(qm->io_base + in sec_show_last_regs_init()
953 static void sec_show_last_regs_uninit(struct hisi_qm *qm) in sec_show_last_regs_uninit() argument
955 struct qm_debug *debug = &qm->debug; in sec_show_last_regs_uninit()
957 if (qm->fun_type == QM_HW_VF || !debug->last_words) in sec_show_last_regs_uninit()
964 static void sec_show_last_dfx_regs(struct hisi_qm *qm) in sec_show_last_dfx_regs() argument
966 struct qm_debug *debug = &qm->debug; in sec_show_last_dfx_regs()
967 struct pci_dev *pdev = qm->pdev; in sec_show_last_dfx_regs()
971 if (qm->fun_type == QM_HW_VF || !debug->last_words) in sec_show_last_dfx_regs()
976 val = readl_relaxed(qm->io_base + sec_dfx_regs[i].offset); in sec_show_last_dfx_regs()
983 static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts) in sec_log_hw_error() argument
986 struct device *dev = &qm->pdev->dev; in sec_log_hw_error()
995 err_val = readl(qm->io_base + in sec_log_hw_error()
1006 static u32 sec_get_hw_err_status(struct hisi_qm *qm) in sec_get_hw_err_status() argument
1008 return readl(qm->io_base + SEC_CORE_INT_STATUS); in sec_get_hw_err_status()
1011 static void sec_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) in sec_clear_hw_err_status() argument
1015 writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE); in sec_clear_hw_err_status()
1016 nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver); in sec_clear_hw_err_status()
1017 writel(nfe, qm->io_base + SEC_RAS_NFE_REG); in sec_clear_hw_err_status()
1020 static void sec_open_axi_master_ooo(struct hisi_qm *qm) in sec_open_axi_master_ooo() argument
1024 val = readl(qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()
1025 writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()
1026 writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()
1029 static void sec_err_info_init(struct hisi_qm *qm) in sec_err_info_init() argument
1031 struct hisi_qm_err_info *err_info = &qm->err_info; in sec_err_info_init()
1034 err_info->ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_CE_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1035 err_info->nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_NFE_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1037 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info, in sec_err_info_init()
1038 SEC_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1039 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info, in sec_err_info_init()
1040 SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1041 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info, in sec_err_info_init()
1042 SEC_QM_RESET_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1043 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info, in sec_err_info_init()
1044 SEC_RESET_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1065 struct hisi_qm *qm = &sec->qm; in sec_pf_probe_init() local
1068 ret = sec_set_user_domain_and_cache(qm); in sec_pf_probe_init()
1072 sec_open_sva_prefetch(qm); in sec_pf_probe_init()
1073 hisi_qm_dev_err_init(qm); in sec_pf_probe_init()
1074 sec_debug_regs_clear(qm); in sec_pf_probe_init()
1075 ret = sec_show_last_regs_init(qm); in sec_pf_probe_init()
1077 pci_err(qm->pdev, "Failed to init last word regs!\n"); in sec_pf_probe_init()
1082 static int sec_pre_store_cap_reg(struct hisi_qm *qm) in sec_pre_store_cap_reg() argument
1085 struct pci_dev *pdev = qm->pdev; in sec_pre_store_cap_reg()
1095 sec_cap[i].cap_val = hisi_qm_get_hw_info(qm, sec_basic_info, in sec_pre_store_cap_reg()
1096 sec_pre_store_caps[i], qm->cap_ver); in sec_pre_store_cap_reg()
1099 qm->cap_tables.dev_cap_table = sec_cap; in sec_pre_store_cap_reg()
1104 static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) in sec_qm_init() argument
1109 qm->pdev = pdev; in sec_qm_init()
1110 qm->ver = pdev->revision; in sec_qm_init()
1111 qm->mode = uacce_mode; in sec_qm_init()
1112 qm->sqe_size = SEC_SQE_SIZE; in sec_qm_init()
1113 qm->dev_name = sec_name; in sec_qm_init()
1115 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) ? in sec_qm_init()
1117 if (qm->fun_type == QM_HW_PF) { in sec_qm_init()
1118 qm->qp_base = SEC_PF_DEF_Q_BASE; in sec_qm_init()
1119 qm->qp_num = pf_q_num; in sec_qm_init()
1120 qm->debug.curr_qm_qp_num = pf_q_num; in sec_qm_init()
1121 qm->qm_list = &sec_devices; in sec_qm_init()
1122 qm->err_ini = &sec_err_ini; in sec_qm_init()
1124 set_bit(QM_MODULE_PARAM, &qm->misc_ctl); in sec_qm_init()
1125 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { in sec_qm_init()
1132 qm->qp_base = SEC_PF_DEF_Q_NUM; in sec_qm_init()
1133 qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM; in sec_qm_init()
1136 ret = hisi_qm_init(qm); in sec_qm_init()
1138 pci_err(qm->pdev, "Failed to init sec qm configures!\n"); in sec_qm_init()
1143 ret = sec_pre_store_cap_reg(qm); in sec_qm_init()
1145 pci_err(qm->pdev, "Failed to pre-store capability registers!\n"); in sec_qm_init()
1146 hisi_qm_uninit(qm); in sec_qm_init()
1150 alg_msk = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH_IDX, SEC_DEV_ALG_BITMAP_LOW_IDX); in sec_qm_init()
1151 ret = hisi_qm_set_algs(qm, alg_msk, sec_dev_algs, ARRAY_SIZE(sec_dev_algs)); in sec_qm_init()
1153 pci_err(qm->pdev, "Failed to set sec algs!\n"); in sec_qm_init()
1154 hisi_qm_uninit(qm); in sec_qm_init()
1160 static void sec_qm_uninit(struct hisi_qm *qm) in sec_qm_uninit() argument
1162 hisi_qm_uninit(qm); in sec_qm_uninit()
1168 struct hisi_qm *qm = &sec->qm; in sec_probe_init() local
1171 if (qm->fun_type == QM_HW_PF) { in sec_probe_init()
1176 if (qm->ver >= QM_HW_V3) { in sec_probe_init()
1178 qm->type_rate = type_rate; in sec_probe_init()
1185 static void sec_probe_uninit(struct hisi_qm *qm) in sec_probe_uninit() argument
1187 if (qm->fun_type == QM_HW_VF) in sec_probe_uninit()
1190 sec_debug_regs_clear(qm); in sec_probe_uninit()
1191 sec_show_last_regs_uninit(qm); in sec_probe_uninit()
1192 sec_close_sva_prefetch(qm); in sec_probe_uninit()
1193 hisi_qm_dev_err_uninit(qm); in sec_probe_uninit()
1199 struct device *dev = &sec->qm.pdev->dev; in sec_iommu_used_check()
1216 struct hisi_qm *qm; in sec_probe() local
1223 qm = &sec->qm; in sec_probe()
1224 ret = sec_qm_init(qm, pdev); in sec_probe()
1239 ret = hisi_qm_start(qm); in sec_probe()
1245 ret = sec_debugfs_init(qm); in sec_probe()
1249 hisi_qm_add_list(qm, &sec_devices); in sec_probe()
1250 ret = hisi_qm_alg_register(qm, &sec_devices, ctx_q_num); in sec_probe()
1256 if (qm->uacce) { in sec_probe()
1257 ret = uacce_register(qm->uacce); in sec_probe()
1264 if (qm->fun_type == QM_HW_PF && vfs_num) { in sec_probe()
1270 hisi_qm_pm_init(qm); in sec_probe()
1275 hisi_qm_alg_unregister(qm, &sec_devices, ctx_q_num); in sec_probe()
1277 hisi_qm_del_list(qm, &sec_devices); in sec_probe()
1278 sec_debugfs_exit(qm); in sec_probe()
1279 hisi_qm_stop(qm, QM_NORMAL); in sec_probe()
1281 sec_probe_uninit(qm); in sec_probe()
1283 sec_qm_uninit(qm); in sec_probe()
1289 struct hisi_qm *qm = pci_get_drvdata(pdev); in sec_remove() local
1291 hisi_qm_pm_uninit(qm); in sec_remove()
1292 hisi_qm_wait_task_finish(qm, &sec_devices); in sec_remove()
1293 hisi_qm_alg_unregister(qm, &sec_devices, ctx_q_num); in sec_remove()
1294 hisi_qm_del_list(qm, &sec_devices); in sec_remove()
1296 if (qm->fun_type == QM_HW_PF && qm->vfs_num) in sec_remove()
1299 sec_debugfs_exit(qm); in sec_remove()
1301 (void)hisi_qm_stop(qm, QM_NORMAL); in sec_remove()
1302 sec_probe_uninit(qm); in sec_remove()
1304 sec_qm_uninit(qm); in sec_remove()