16 #define HPRE_CTRL_CNT_CLR_CE_BIT	BIT(0)
17 #define HPRE_CTRL_CNT_CLR_CE		0x301000
18 #define HPRE_FSM_MAX_CNT		0x301008
19 #define HPRE_VFG_AXQOS			0x30100c
20 #define HPRE_VFG_AXCACHE		0x301010
21 #define HPRE_RDCHN_INI_CFG		0x301014
22 #define HPRE_AWUSR_FP_CFG		0x301018
23 #define HPRE_BD_ENDIAN			0x301020
24 #define HPRE_ECC_BYPASS			0x301024
25 #define HPRE_RAS_WIDTH_CFG		0x301028
26 #define HPRE_POISON_BYPASS		0x30102c
27 #define HPRE_BD_ARUSR_CFG		0x301030
28 #define HPRE_BD_AWUSR_CFG		0x301034
29 #define HPRE_TYPES_ENB			0x301038
30 #define HPRE_RSA_ENB			BIT(0)
32 #define HPRE_DATA_RUSER_CFG		0x30103c
33 #define HPRE_DATA_WUSER_CFG		0x301040
34 #define HPRE_INT_MASK			0x301400
35 #define HPRE_INT_STATUS			0x301800
36 #define HPRE_HAC_INT_MSK		0x301400
37 #define HPRE_HAC_RAS_CE_ENB		0x301410
38 #define HPRE_HAC_RAS_NFE_ENB		0x301414
39 #define HPRE_HAC_RAS_FE_ENB		0x301418
40 #define HPRE_HAC_INT_SET		0x301500
41 #define HPRE_RNG_TIMEOUT_NUM		0x301A34
42 #define HPRE_CORE_INT_ENABLE		0
43 #define HPRE_RDCHN_INI_ST		0x301a00
44 #define HPRE_CLSTR_BASE			0x302000
45 #define HPRE_CORE_EN_OFFSET		0x04
46 #define HPRE_CORE_INI_CFG_OFFSET	0x20
47 #define HPRE_CORE_INI_STATUS_OFFSET	0x80
48 #define HPRE_CORE_HTBT_WARN_OFFSET	0x8c
49 #define HPRE_CORE_IS_SCHD_OFFSET	0x90
51 #define HPRE_RAS_CE_ENB			0x301410
52 #define HPRE_RAS_NFE_ENB		0x301414
53 #define HPRE_RAS_FE_ENB			0x301418
54 #define HPRE_OOO_SHUTDOWN_SEL		0x301a3c
55 #define HPRE_HAC_RAS_FE_ENABLE		0
60 #define HPRE_HAC_ECC1_CNT		0x301a04
61 #define HPRE_HAC_ECC2_CNT		0x301a08
62 #define HPRE_HAC_SOURCE_INT		0x301600
63 #define HPRE_CLSTR_ADDR_INTRVL		0x1000
64 #define HPRE_CLUSTER_INQURY		0x100
65 #define HPRE_CLSTR_ADDR_INQRY_RSLT	0x104
70 #define PCI_DEVICE_ID_HUAWEI_HPRE_PF	0xa258
72 #define HPRE_QM_AXI_CFG_MASK		GENMASK(15, 0)
73 #define HPRE_QM_VFG_AX_MASK		GENMASK(7, 0)
74 #define HPRE_BD_USR_MASK		GENMASK(1, 0)
75 #define HPRE_PREFETCH_CFG		0x301130
76 #define HPRE_SVA_PREFTCH_DFX		0x30115C
77 #define HPRE_PREFETCH_ENABLE		(~(BIT(0) | BIT(30)))
82 #define HPRE_CLKGATE_CTL		0x301a10
83 #define HPRE_PEH_CFG_AUTO_GATE		0x301a2c
84 #define HPRE_CLUSTER_DYN_CTL		0x302010
85 #define HPRE_CORE_SHB_CFG		0x302088
86 #define HPRE_CLKGATE_CTL_EN		BIT(0)
87 #define HPRE_PEH_CFG_AUTO_GATE_EN	BIT(0)
88 #define HPRE_CLUSTER_DYN_CTL_EN		BIT(0)
91 #define HPRE_AM_OOO_SHUTDOWN_ENB	0x301044
92 #define HPRE_AM_OOO_SHUTDOWN_ENABLE	BIT(0)
108 #define HPRE_DFX_BASE		0x301000
109 #define HPRE_DFX_COMMON1		0x301400
110 #define HPRE_DFX_COMMON2		0x301A00
111 #define HPRE_DFX_CORE		0x302000
112 #define HPRE_DFX_BASE_LEN		0x55
113 #define HPRE_DFX_COMMON1_LEN		0x41
114 #define HPRE_DFX_COMMON2_LEN		0xE
115 #define HPRE_DFX_CORE_LEN		0x43
122 	{ 0, }
134 		.alg_msk = BIT(0),
198 	{HPRE_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C37, 0x7C37},
199 	{HPRE_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC37, 0x6C37},
200 	{HPRE_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C37},
201 	{HPRE_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8},
202 	{HPRE_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0x1FFFC3E},
203 	{HPRE_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0xBFFC3E},
204 	{HPRE_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x22, 0xBFFC3E},
205 	{HPRE_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1},
206 	{HPRE_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x0,  0x4, 0x1},
207 	{HPRE_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x0, 0x2, 0x2},
208 	{HPRE_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x0, 0x8, 0xA},
209 	{HPRE_CLUSTER_CORE_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x0, 0x2, 0xA},
210 	{HPRE_CORE_ENABLE_BITMAP_CAP, 0x3140, 0, GENMASK(31, 0), 0x0, 0xF, 0x3FF},
211 	{HPRE_DRV_ALG_BITMAP_CAP, 0x3144, 0, GENMASK(31, 0), 0x0, 0x03, 0x27},
212 	{HPRE_DEV_ALG_BITMAP_CAP, 0x3148, 0, GENMASK(31, 0), 0x0, 0x03, 0x7F},
213 	{HPRE_CORE1_ALG_BITMAP_CAP, 0x314c, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
214 	{HPRE_CORE2_ALG_BITMAP_CAP, 0x3150, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
215 	{HPRE_CORE3_ALG_BITMAP_CAP, 0x3154, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
216 	{HPRE_CORE4_ALG_BITMAP_CAP, 0x3158, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
217 	{HPRE_CORE5_ALG_BITMAP_CAP, 0x315c, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
218 	{HPRE_CORE6_ALG_BITMAP_CAP, 0x3160, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
219 	{HPRE_CORE7_ALG_BITMAP_CAP, 0x3164, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
220 	{HPRE_CORE8_ALG_BITMAP_CAP, 0x3168, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
221 	{HPRE_CORE9_ALG_BITMAP_CAP, 0x316c, 0, GENMASK(31, 0), 0x0, 0x10, 0x10},
222 	{HPRE_CORE10_ALG_BITMAP_CAP, 0x3170, 0, GENMASK(31, 0), 0x0, 0x10, 0x10}
226 	HPRE_CLUSTER_NUM_CAP_IDX = 0x0,
241 		.int_msk = BIT(0),
377 	return 0;  in hpre_diff_regs_show()
386 	return 0;  in hpre_com_regs_show()
395 	return 0;  in hpre_cluster_regs_show()
406  * uacce_mode = 0 means hpre only register to crypto,
437 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
449 	 * type: 0 - RSA/DH. algorithm supported in V2,  in hpre_create_qp()
492 				0, HPRE_VIA_MSI_DSM, NULL);  in hpre_cfg_by_dsm()
500 	return 0;  in hpre_cfg_by_dsm()
509 	u32 val = 0;  in hpre_set_cluster()
514 	for (i = 0; i < clusters_num; i++) {  in hpre_set_cluster()
520 		writel(0x1, qm->io_base + offset + HPRE_CORE_INI_CFG);  in hpre_set_cluster()
534 	return 0;  in hpre_set_cluster()
662 	writel(0x0, qm->io_base + HPRE_BD_ENDIAN);  in hpre_set_user_domain_and_cache()
663 	writel(0x0, qm->io_base + HPRE_POISON_BYPASS);  in hpre_set_user_domain_and_cache()
664 	writel(0x0, qm->io_base + HPRE_ECC_BYPASS);  in hpre_set_user_domain_and_cache()
668 	writel(0x1, qm->io_base + HPRE_RDCHN_INI_CFG);  in hpre_set_user_domain_and_cache()
670 			val & BIT(0),  in hpre_set_user_domain_and_cache()
707 	for (i = 0; i < clusters_num; i++) {  in hpre_cnt_regs_clear()
709 		writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY);  in hpre_cnt_regs_clear()
713 	writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE);  in hpre_cnt_regs_clear()
729 		val2 = 0x0;  in hpre_master_ooo_ctrl()
794 	if (val != 1 && val != 0)  in hpre_clear_enable_write()
801 	return 0;  in hpre_clear_enable_write()
869 	if (*pos != 0)  in hpre_ctrl_debug_write()
870 		return 0;  in hpre_ctrl_debug_write()
877 	if (len < 0)  in hpre_ctrl_debug_write()
880 	tbuf[len] = '\0';  in hpre_ctrl_debug_write()
881 	if (kstrtoul(tbuf, 0, &val))  in hpre_ctrl_debug_write()
924 	return 0;  in hpre_debugfs_atomic64_get()
934 		atomic64_set(&hpre_dfx[HPRE_OVER_THRHLD_CNT].value, 0);  in hpre_debugfs_atomic64_set()
941 	return 0;  in hpre_debugfs_atomic64_set()
969 	return 0;  in hpre_create_debugfs_file()
989 	return 0;  in hpre_pf_comm_regs_debugfs_init()
1002 	for (i = 0; i < clusters_num; i++) {  in hpre_cluster_debugfs_init()
1025 	return 0;  in hpre_cluster_debugfs_init()
1053 	for (i = 0; i < HPRE_DFX_FILE_NUM; i++) {  in hpre_dfx_debug_init()
1090 	return 0;  in hpre_debugfs_init()
1116 	for (i = 0; i < size; i++) {  in hpre_pre_store_cap_reg()
1130 	return 0;  in hpre_pre_store_cap_reg()
1200 	for (i = 0; i < com_dfx_regs_num; i++)  in hpre_show_last_regs_init()
1204 	for (i = 0; i < clusters_num; i++) {  in hpre_show_last_regs_init()
1206 		for (j = 0; j < cluster_dfx_regs_num; j++) {  in hpre_show_last_regs_init()
1213 	return 0;  in hpre_show_last_regs_init()
1242 	for (i = 0; i < com_dfx_regs_num; i++) {  in hpre_show_last_dfx_regs()
1245 			pci_info(pdev, "Common_core:%s \t= 0x%08x => 0x%08x\n",  in hpre_show_last_dfx_regs()
1250 	for (i = 0; i < clusters_num; i++) {  in hpre_show_last_dfx_regs()
1252 		for (j = 0; j <  cluster_dfx_regs_num; j++) {  in hpre_show_last_dfx_regs()
1257 				pci_info(pdev, "cluster-%d:%s \t= 0x%08x => 0x%08x\n",  in hpre_show_last_dfx_regs()
1270 			dev_warn(dev, "%s [error status=0x%x] found\n",  in hpre_log_hw_error()
1364 		/* Enable shaper type 0 */  in hpre_probe_init()
1371 	return 0;  in hpre_probe_init()
1380 	qm->debug.curr_qm_qp_num = 0;  in hpre_probe_uninit()
1419 	if (ret < 0) {  in hpre_probe()
1434 		if (ret < 0)  in hpre_probe()
1440 	return 0;  in hpre_probe()