507 				 unsigned int *seq_size)  in cc_setup_readiv_desc()  argument
527 		hw_desc_init(&desc[*seq_size]);  in cc_setup_readiv_desc()
528 		set_dout_dlli(&desc[*seq_size], iv_dma_addr, ivsize, NS_BIT, 1);  in cc_setup_readiv_desc()
529 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_readiv_desc()
530 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_readiv_desc()
531 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_readiv_desc()
534 			set_setup_mode(&desc[*seq_size], SETUP_WRITE_STATE1);  in cc_setup_readiv_desc()
536 			set_setup_mode(&desc[*seq_size], SETUP_WRITE_STATE0);  in cc_setup_readiv_desc()
538 		set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);  in cc_setup_readiv_desc()
539 		(*seq_size)++;  in cc_setup_readiv_desc()
544 		hw_desc_init(&desc[*seq_size]);  in cc_setup_readiv_desc()
545 		set_setup_mode(&desc[*seq_size], SETUP_WRITE_STATE1);  in cc_setup_readiv_desc()
546 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_readiv_desc()
547 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_readiv_desc()
548 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_readiv_desc()
549 		set_dout_dlli(&desc[*seq_size], iv_dma_addr, CC_AES_BLOCK_SIZE,  in cc_setup_readiv_desc()
551 		set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);  in cc_setup_readiv_desc()
552 		(*seq_size)++;  in cc_setup_readiv_desc()
564 				 unsigned int *seq_size)  in cc_setup_state_desc()  argument
581 		hw_desc_init(&desc[*seq_size]);  in cc_setup_state_desc()
582 		set_din_type(&desc[*seq_size], DMA_DLLI, iv_dma_addr, ivsize,  in cc_setup_state_desc()
584 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_state_desc()
585 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_state_desc()
586 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_state_desc()
589 			set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1);  in cc_setup_state_desc()
591 			set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE0);  in cc_setup_state_desc()
593 		(*seq_size)++;  in cc_setup_state_desc()
608 				 unsigned int *seq_size)  in cc_setup_xex_state_desc()  argument
635 		hw_desc_init(&desc[*seq_size]);  in cc_setup_xex_state_desc()
636 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_xex_state_desc()
637 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_xex_state_desc()
639 			set_hw_crypto_key(&desc[*seq_size],  in cc_setup_xex_state_desc()
642 			set_din_type(&desc[*seq_size], DMA_DLLI,  in cc_setup_xex_state_desc()
646 		set_xex_data_unit_size(&desc[*seq_size], nbytes);  in cc_setup_xex_state_desc()
647 		set_flow_mode(&desc[*seq_size], S_DIN_to_AES2);  in cc_setup_xex_state_desc()
648 		set_key_size_aes(&desc[*seq_size], key_len);  in cc_setup_xex_state_desc()
649 		set_setup_mode(&desc[*seq_size], SETUP_LOAD_XEX_KEY);  in cc_setup_xex_state_desc()
650 		(*seq_size)++;  in cc_setup_xex_state_desc()
653 		hw_desc_init(&desc[*seq_size]);  in cc_setup_xex_state_desc()
654 		set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1);  in cc_setup_xex_state_desc()
655 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_xex_state_desc()
656 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_xex_state_desc()
657 		set_key_size_aes(&desc[*seq_size], key_len);  in cc_setup_xex_state_desc()
658 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_xex_state_desc()
659 		set_din_type(&desc[*seq_size], DMA_DLLI, iv_dma_addr,  in cc_setup_xex_state_desc()
661 		(*seq_size)++;  in cc_setup_xex_state_desc()
685 			      unsigned int *seq_size)  in cc_setup_key_desc()  argument
703 		hw_desc_init(&desc[*seq_size]);  in cc_setup_key_desc()
704 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_key_desc()
705 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_key_desc()
709 			set_key_size_aes(&desc[*seq_size], key_len);  in cc_setup_key_desc()
710 			set_cpp_crypto_key(&desc[*seq_size], ctx_p->cpp.slot);  in cc_setup_key_desc()
715 					set_hw_crypto_key(&desc[*seq_size],  in cc_setup_key_desc()
725 					set_din_type(&desc[*seq_size], DMA_DLLI,  in cc_setup_key_desc()
729 				set_key_size_aes(&desc[*seq_size], key_len);  in cc_setup_key_desc()
732 				set_din_type(&desc[*seq_size], DMA_DLLI,  in cc_setup_key_desc()
734 				set_key_size_des(&desc[*seq_size], key_len);  in cc_setup_key_desc()
736 			set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0);  in cc_setup_key_desc()
738 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_key_desc()
739 		(*seq_size)++;  in cc_setup_key_desc()
744 		hw_desc_init(&desc[*seq_size]);  in cc_setup_key_desc()
745 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_key_desc()
746 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_key_desc()
748 			set_hw_crypto_key(&desc[*seq_size],  in cc_setup_key_desc()
751 			set_din_type(&desc[*seq_size], DMA_DLLI, key_dma_addr,  in cc_setup_key_desc()
754 		set_key_size_aes(&desc[*seq_size], (key_len / 2));  in cc_setup_key_desc()
755 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_key_desc()
756 		set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0);  in cc_setup_key_desc()
757 		(*seq_size)++;  in cc_setup_key_desc()
768 			       struct cc_hw_desc desc[], unsigned int *seq_size)  in cc_setup_mlli_desc()  argument
779 		hw_desc_init(&desc[*seq_size]);  in cc_setup_mlli_desc()
780 		set_din_type(&desc[*seq_size], DMA_DLLI,  in cc_setup_mlli_desc()
783 		set_dout_sram(&desc[*seq_size],  in cc_setup_mlli_desc()
786 		set_flow_mode(&desc[*seq_size], BYPASS);  in cc_setup_mlli_desc()
787 		(*seq_size)++;  in cc_setup_mlli_desc()
795 			       unsigned int *seq_size)  in cc_setup_flow_desc()  argument
809 		hw_desc_init(&desc[*seq_size]);  in cc_setup_flow_desc()
810 		set_din_type(&desc[*seq_size], DMA_DLLI, sg_dma_address(src),  in cc_setup_flow_desc()
812 		set_dout_dlli(&desc[*seq_size], sg_dma_address(dst),  in cc_setup_flow_desc()
815 			set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);  in cc_setup_flow_desc()
817 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_flow_desc()
818 		(*seq_size)++;  in cc_setup_flow_desc()
820 		hw_desc_init(&desc[*seq_size]);  in cc_setup_flow_desc()
821 		set_din_type(&desc[*seq_size], DMA_MLLI,  in cc_setup_flow_desc()
828 			set_dout_mlli(&desc[*seq_size],  in cc_setup_flow_desc()
837 			set_dout_mlli(&desc[*seq_size],  in cc_setup_flow_desc()
845 			set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);  in cc_setup_flow_desc()
847 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_flow_desc()
848 		(*seq_size)++;  in cc_setup_flow_desc()