Lines Matching +full:offset +full:- +full:x
1 // SPDX-License-Identifier: GPL-2.0
15 * - NPS packet ring, AQMQ ring and ZQMQ ring
24 * nps_pkt_slc_isr - IRQ handler for NPS solicit port
32 struct nitrox_cmdq *cmdq = qvec->cmdq; in nps_pkt_slc_isr()
34 slc_cnts.value = readq(cmdq->compl_cnt_csr_addr); in nps_pkt_slc_isr()
37 tasklet_hi_schedule(&qvec->resp_tasklet); in nps_pkt_slc_isr()
50 dev_err_ratelimited(DEV(ndev), "NSP_CORE_INT 0x%016llx\n", value); in clear_nps_core_err_intr()
56 unsigned long value, offset; in clear_nps_pkt_err_intr() local
60 dev_err_ratelimited(DEV(ndev), "NPS_PKT_INT 0x%016llx\n", in clear_nps_pkt_err_intr()
64 offset = NPS_PKT_SLC_ERR_TYPE; in clear_nps_pkt_err_intr()
65 value = nitrox_read_csr(ndev, offset); in clear_nps_pkt_err_intr()
66 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
68 "NPS_PKT_SLC_ERR_TYPE 0x%016lx\n", value); in clear_nps_pkt_err_intr()
70 offset = NPS_PKT_SLC_RERR_LO; in clear_nps_pkt_err_intr()
71 value = nitrox_read_csr(ndev, offset); in clear_nps_pkt_err_intr()
72 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
78 "NPS_PKT_SLC_RERR_LO 0x%016lx\n", value); in clear_nps_pkt_err_intr()
80 offset = NPS_PKT_SLC_RERR_HI; in clear_nps_pkt_err_intr()
81 value = nitrox_read_csr(ndev, offset); in clear_nps_pkt_err_intr()
82 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
84 "NPS_PKT_SLC_RERR_HI 0x%016lx\n", value); in clear_nps_pkt_err_intr()
88 offset = NPS_PKT_IN_ERR_TYPE; in clear_nps_pkt_err_intr()
89 value = nitrox_read_csr(ndev, offset); in clear_nps_pkt_err_intr()
90 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
92 "NPS_PKT_IN_ERR_TYPE 0x%016lx\n", value); in clear_nps_pkt_err_intr()
93 offset = NPS_PKT_IN_RERR_LO; in clear_nps_pkt_err_intr()
94 value = nitrox_read_csr(ndev, offset); in clear_nps_pkt_err_intr()
95 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
101 "NPS_PKT_IN_RERR_LO 0x%016lx\n", value); in clear_nps_pkt_err_intr()
103 offset = NPS_PKT_IN_RERR_HI; in clear_nps_pkt_err_intr()
104 value = nitrox_read_csr(ndev, offset); in clear_nps_pkt_err_intr()
105 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
107 "NPS_PKT_IN_RERR_HI 0x%016lx\n", value); in clear_nps_pkt_err_intr()
117 dev_err_ratelimited(DEV(ndev), "POM_INT 0x%016llx\n", value); in clear_pom_err_intr()
126 dev_err_ratelimited(DEV(ndev), "PEM(0)_INT 0x%016llx\n", value); in clear_pem_err_intr()
132 u64 value, offset; in clear_lbc_err_intr() local
136 dev_err_ratelimited(DEV(ndev), "LBC_INT 0x%016llx\n", lbc_int.value); in clear_lbc_err_intr()
140 offset = EFL_CORE_VF_ERR_INT0X(i); in clear_lbc_err_intr()
141 value = nitrox_read_csr(ndev, offset); in clear_lbc_err_intr()
142 nitrox_write_csr(ndev, offset, value); in clear_lbc_err_intr()
143 offset = EFL_CORE_VF_ERR_INT1X(i); in clear_lbc_err_intr()
144 value = nitrox_read_csr(ndev, offset); in clear_lbc_err_intr()
145 nitrox_write_csr(ndev, offset, value); in clear_lbc_err_intr()
155 offset = LBC_PLM_VF1_64_INT; in clear_lbc_err_intr()
156 value = nitrox_read_csr(ndev, offset); in clear_lbc_err_intr()
157 nitrox_write_csr(ndev, offset, value); in clear_lbc_err_intr()
158 offset = LBC_PLM_VF65_128_INT; in clear_lbc_err_intr()
159 value = nitrox_read_csr(ndev, offset); in clear_lbc_err_intr()
160 nitrox_write_csr(ndev, offset, value); in clear_lbc_err_intr()
164 offset = LBC_ELM_VF1_64_INT; in clear_lbc_err_intr()
165 value = nitrox_read_csr(ndev, offset); in clear_lbc_err_intr()
166 nitrox_write_csr(ndev, offset, value); in clear_lbc_err_intr()
167 offset = LBC_ELM_VF65_128_INT; in clear_lbc_err_intr()
168 value = nitrox_read_csr(ndev, offset); in clear_lbc_err_intr()
169 nitrox_write_csr(ndev, offset, value); in clear_lbc_err_intr()
180 u64 value, offset; in clear_efl_err_intr() local
182 offset = EFL_CORE_INTX(i); in clear_efl_err_intr()
183 core_int.value = nitrox_read_csr(ndev, offset); in clear_efl_err_intr()
184 nitrox_write_csr(ndev, offset, core_int.value); in clear_efl_err_intr()
185 dev_err_ratelimited(DEV(ndev), "ELF_CORE(%d)_INT 0x%016llx\n", in clear_efl_err_intr()
188 offset = EFL_CORE_SE_ERR_INTX(i); in clear_efl_err_intr()
189 value = nitrox_read_csr(ndev, offset); in clear_efl_err_intr()
190 nitrox_write_csr(ndev, offset, value); in clear_efl_err_intr()
201 dev_err_ratelimited(DEV(ndev), "BMI_INT 0x%016llx\n", value); in clear_bmi_err_intr()
207 struct nitrox_device *ndev = qvec->ndev; in nps_core_int_tasklet()
210 if (ndev->mode == __NDEV_MODE_PF) { in nps_core_int_tasklet()
220 * nps_core_int_isr - interrupt handler for NITROX errors and
226 struct nitrox_device *ndev = qvec->ndev; in nps_core_int_isr()
265 struct pci_dev *pdev = ndev->pdev; in nitrox_unregister_interrupts()
268 for (i = 0; i < ndev->num_vecs; i++) { in nitrox_unregister_interrupts()
272 qvec = ndev->qvec + i; in nitrox_unregister_interrupts()
273 if (!qvec->valid) in nitrox_unregister_interrupts()
281 tasklet_disable(&qvec->resp_tasklet); in nitrox_unregister_interrupts()
282 tasklet_kill(&qvec->resp_tasklet); in nitrox_unregister_interrupts()
283 qvec->valid = false; in nitrox_unregister_interrupts()
285 kfree(ndev->qvec); in nitrox_unregister_interrupts()
286 ndev->qvec = NULL; in nitrox_unregister_interrupts()
292 struct pci_dev *pdev = ndev->pdev; in nitrox_register_interrupts()
298 * PF MSI-X vectors in nitrox_register_interrupts()
315 /* Enable MSI-X */ in nitrox_register_interrupts()
321 ndev->num_vecs = nr_vecs; in nitrox_register_interrupts()
323 ndev->qvec = kcalloc(nr_vecs, sizeof(*qvec), GFP_KERNEL); in nitrox_register_interrupts()
324 if (!ndev->qvec) { in nitrox_register_interrupts()
326 return -ENOMEM; in nitrox_register_interrupts()
330 for (i = PKT_RING_MSIX_BASE; i < (nr_vecs - 1); i += NR_RING_VECTORS) { in nitrox_register_interrupts()
331 qvec = &ndev->qvec[i]; in nitrox_register_interrupts()
333 qvec->ring = i / NR_RING_VECTORS; in nitrox_register_interrupts()
334 if (qvec->ring >= ndev->nr_queues) in nitrox_register_interrupts()
337 qvec->cmdq = &ndev->pkt_inq[qvec->ring]; in nitrox_register_interrupts()
338 snprintf(qvec->name, IRQ_NAMESZ, "nitrox-pkt%d", qvec->ring); in nitrox_register_interrupts()
341 ret = request_irq(vec, nps_pkt_slc_isr, 0, qvec->name, qvec); in nitrox_register_interrupts()
344 qvec->ring); in nitrox_register_interrupts()
347 cpu = qvec->ring % num_online_cpus(); in nitrox_register_interrupts()
350 tasklet_init(&qvec->resp_tasklet, pkt_slc_resp_tasklet, in nitrox_register_interrupts()
352 qvec->valid = true; in nitrox_register_interrupts()
357 qvec = &ndev->qvec[i]; in nitrox_register_interrupts()
358 qvec->ndev = ndev; in nitrox_register_interrupts()
360 snprintf(qvec->name, IRQ_NAMESZ, "nitrox-core-int%d", i); in nitrox_register_interrupts()
363 ret = request_irq(vec, nps_core_int_isr, 0, qvec->name, qvec); in nitrox_register_interrupts()
365 dev_err(DEV(ndev), "irq failed for nitrox-core-int%d\n", i); in nitrox_register_interrupts()
371 tasklet_init(&qvec->resp_tasklet, nps_core_int_tasklet, in nitrox_register_interrupts()
373 qvec->valid = true; in nitrox_register_interrupts()
384 struct pci_dev *pdev = ndev->pdev; in nitrox_sriov_unregister_interrupts()
387 for (i = 0; i < ndev->num_vecs; i++) { in nitrox_sriov_unregister_interrupts()
391 qvec = ndev->qvec + i; in nitrox_sriov_unregister_interrupts()
392 if (!qvec->valid) in nitrox_sriov_unregister_interrupts()
395 vec = ndev->iov.msix.vector; in nitrox_sriov_unregister_interrupts()
399 tasklet_disable(&qvec->resp_tasklet); in nitrox_sriov_unregister_interrupts()
400 tasklet_kill(&qvec->resp_tasklet); in nitrox_sriov_unregister_interrupts()
401 qvec->valid = false; in nitrox_sriov_unregister_interrupts()
403 kfree(ndev->qvec); in nitrox_sriov_unregister_interrupts()
404 ndev->qvec = NULL; in nitrox_sriov_unregister_interrupts()
410 struct pci_dev *pdev = ndev->pdev; in nitrox_sriov_register_interupts()
417 * for PF in SR-IOV mode. in nitrox_sriov_register_interupts()
419 ndev->iov.msix.entry = NON_RING_MSIX_BASE; in nitrox_sriov_register_interupts()
420 ret = pci_enable_msix_exact(pdev, &ndev->iov.msix, NR_NON_RING_VECTORS); in nitrox_sriov_register_interupts()
422 dev_err(DEV(ndev), "failed to allocate nps-core-int%d\n", in nitrox_sriov_register_interupts()
430 return -ENOMEM; in nitrox_sriov_register_interupts()
432 qvec->ndev = ndev; in nitrox_sriov_register_interupts()
434 ndev->qvec = qvec; in nitrox_sriov_register_interupts()
435 ndev->num_vecs = NR_NON_RING_VECTORS; in nitrox_sriov_register_interupts()
436 snprintf(qvec->name, IRQ_NAMESZ, "nitrox-core-int%d", in nitrox_sriov_register_interupts()
439 vec = ndev->iov.msix.vector; in nitrox_sriov_register_interupts()
440 ret = request_irq(vec, nps_core_int_isr, 0, qvec->name, qvec); in nitrox_sriov_register_interupts()
442 dev_err(DEV(ndev), "irq failed for nitrox-core-int%d\n", in nitrox_sriov_register_interupts()
449 tasklet_init(&qvec->resp_tasklet, nps_core_int_tasklet, in nitrox_sriov_register_interupts()
451 qvec->valid = true; in nitrox_sriov_register_interupts()