cavium/nitrox/nitrox_csr.h

1 /* SPDX-License-Identifier: GPL-2.0 */
151 /* Mailbox PF->VF PF Accessible Data registers */
206  * struct ucd_core_eid_ucode_block_num - Core Eid to Ucode Blk Mapping Registers
226  * struct aqm_grp_execmsk_lo - Available AE engines for the group
243  * struct aqm_grp_execmsk_hi - Available AE engines for the group
260  * struct aqmq_drbl - AQM Queue Doorbell Counter Registers
277  * struct aqmq_qsz - AQM Queue Host Queue Size Registers
295  * struct aqmq_cmp_thr - AQM Queue Commands Completed Threshold Registers
313  * struct aqmq_cmp_cnt - AQM Queue Commands Completed Count Registers
337  * struct aqmq_en - AQM Queue Enable Registers
354  * struct aqmq_activity_stat - AQM Queue Activity Status Registers
371  * struct emu_fuse_map - EMU Fuse Map Registers
397  * struct emu_se_enable - Symmetric Engine Enable Registers
415  * struct emu_ae_enable - EMU Asymmetric engines.
433  * struct emu_wd_int_ena_w1s - EMU Interrupt Enable Registers
455  * struct emu_ge_int_ena_w1s - EMU Interrupt Enable set registers
477  * struct nps_pkt_slc_ctl - Solicited Packet Out Control Registers
502  * struct nps_pkt_slc_cnts - Solicited Packet Out Count Registers
546  * struct nps_pkt_slc_int_levels - Solicited Packet Out Interrupt Levels
571  * struct nps_pkt_inst - NPS Packet Interrupt Register
611  * struct nps_pkt_in_done_cnts - Input instruction ring counts registers
630  * @resend: A write of 1 will resend an MSI-X interrupt message if any
670  * struct nps_pkt_in_instr_ctl - Input Instruction Ring Control Registers.
671  * @is64b: If 1, the ring uses 64-byte instructions. If 0, the
672  *   ring uses 32-byte instructions.
691  * struct nps_pkt_in_instr_rsize - Input instruction ring size registers
708  * struct nps_pkt_in_instr_baoff_dbell - Input instruction ring
730  * struct nps_core_int_ena_w1s - NPS core interrupt enable set register
772  * struct nps_core_gbl_vfcfg - Global VF Configuration Register.
818  * struct nps_core_int_active - NPS Core Interrupt Active Register
819  * @resend: Resend MSI-X interrupt if needs to handle interrupts
827  * @bmi: Set when any BMI_INT bit is set or when any non-RO
831  * @efl: Set when any EFL_INT RO bit is set or when any non-RO EFL_INT
834  * @lbc: Set when any LBC_INT RO bit is set or when any non-RO LBC_INT
836  * @pem: Set when any PEM(0)_INT RO bit is set or when any non-RO
839  * @zctl: Set when any ZIP_INT RO bit is set or when any non-RO ZIP_INT
843  * @nps_core: Set when any NPS_CORE_INT RO bit is set or when non-RO
894  * struct efl_core_int - EFL Interrupt Registers
902  * @dbe: Double-bit error occurred in EFL
903  * @sbe: Single-bit error occurred in EFL
904  * @d_left: Asserted when new POM-Header-BMI-data is
907  * @len_ovr: Asserted when an Exec-Read is issued that is more than
936  * struct efl_core_int_ena_w1s - EFL core interrupt enable set register
964  * struct efl_rnm_ctl_status - RNM Control and Status Register
998  * struct bmi_ctl - BMI control register
1043  * struct bmi_int_ena_w1s - BMI interrupt enable set register
1105  * struct bmo_ctl2 - BMO Control2 Register
1142  * struct pom_int_ena_w1s - POM interrupt enable set register
1166  * struct lbc_inval_ctl - LBC invalidation control register
1195  * struct lbc_int_ena_w1s - LBC interrupt enable set register
1232  * struct lbc_int - LBC interrupt summary register
1247  *   a cacheline in LBC has non-zero usage and the context
1399  *    BWADJ value