allwinner/sun4i-ss/sun4i-ss.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * sun4i-ss.h - hardware cryptographic accelerator for Allwinner A20 SoC
5  * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
14 #include <linux/clk.h>
65 /* PRNG generator mode - bit 15 */
72 /* SS operation mode - bits 12-13 */
77 /* Counter width for CNT mode - bits 10-11 */
78 #define SS_CNT_16BITS		(0 << 10)
79 #define SS_CNT_32BITS		(1 << 10)
80 #define SS_CNT_64BITS		(2 << 10)
82 /* Key size for AES - bits 8-9 */
87 /* Operation direction - bit 7 */
91 /* SS Method - bits 4-6 */
99 /* Data end bit - bit 2 */
102 /* PRNG start bit - bit 1 */
105 /* SS Enable bit - bit 0 */
110 /* RX FIFO status - bit 30 */
113 /* RX FIFO empty spaces - bits 24-29 */
116 /* TX FIFO status - bit 22 */
119 /* TX FIFO available spaces - bits 16-21 */
126 #define SS_RXFIFO_EMP_INT_PENDING	(1 << 10)
135  * struct ss_variant - Describe SS hardware variant
136  * @sha1_in_be:		The SHA1 digest is given by SS in BE, and so need to be inverted.
146 	struct clk *busclk;
147 	struct clk *ssclk;