Lines Matching +full:0 +full:x03c00000
27 #define relaxed_check 0
40 [27, 25:22] (in MSR 0x2a) */ in pentium3_get_frequency()
42 { 30, 0x01 }, in pentium3_get_frequency()
43 { 35, 0x05 }, in pentium3_get_frequency()
44 { 40, 0x02 }, in pentium3_get_frequency()
45 { 45, 0x06 }, in pentium3_get_frequency()
46 { 50, 0x00 }, in pentium3_get_frequency()
47 { 55, 0x04 }, in pentium3_get_frequency()
48 { 60, 0x0b }, in pentium3_get_frequency()
49 { 65, 0x0f }, in pentium3_get_frequency()
50 { 70, 0x09 }, in pentium3_get_frequency()
51 { 75, 0x0d }, in pentium3_get_frequency()
52 { 80, 0x0a }, in pentium3_get_frequency()
53 { 85, 0x26 }, in pentium3_get_frequency()
54 { 90, 0x20 }, in pentium3_get_frequency()
55 { 100, 0x2b }, in pentium3_get_frequency()
56 { 0, 0xff } /* error or unknown value */ in pentium3_get_frequency()
63 (in MSR 0x2a) */ in pentium3_get_frequency()
65 { 66, 0x0 }, in pentium3_get_frequency()
66 { 100, 0x2 }, in pentium3_get_frequency()
67 { 133, 0x1 }, in pentium3_get_frequency()
68 { 0, 0xff} in pentium3_get_frequency()
72 int i = 0, j = 0; in pentium3_get_frequency()
74 /* read MSR 0x2a - we only need the low 32 bits */ in pentium3_get_frequency()
76 pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp); in pentium3_get_frequency()
80 msr_tmp &= 0x00c0000; in pentium3_get_frequency()
83 if (msr_decode_fsb[i].bitmap == 0xff) in pentium3_get_frequency()
84 return 0; in pentium3_get_frequency()
91 msr_lo &= 0x03c00000; in pentium3_get_frequency()
93 msr_lo &= 0x0bc00000; in pentium3_get_frequency()
96 if (msr_decode_mult[j].bitmap == 0xff) in pentium3_get_frequency()
97 return 0; in pentium3_get_frequency()
113 pr_debug("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp); in pentiumM_get_frequency()
116 if (msr_lo & 0x00040000) { in pentiumM_get_frequency()
117 printk(KERN_DEBUG PFX "PM - invalid FSB: 0x%x 0x%x\n", in pentiumM_get_frequency()
119 return 0; in pentiumM_get_frequency()
122 msr_tmp = (msr_lo >> 22) & 0x1f; in pentiumM_get_frequency()
123 pr_debug("bits 22-26 are 0x%x, speed is %u\n", in pentiumM_get_frequency()
131 u32 fsb = 0; in pentium_core_get_frequency()
137 switch (msr_lo & 0x07) { in pentium_core_get_frequency()
150 case 0: in pentium_core_get_frequency()
161 pr_debug("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", in pentium_core_get_frequency()
164 msr_tmp = (msr_lo >> 22) & 0x1f; in pentium_core_get_frequency()
165 pr_debug("bits 22-26 are 0x%x, speed is %u\n", in pentium_core_get_frequency()
177 unsigned int fsb = 0; in pentium4_get_frequency()
181 /* Pentium 4 Model 0 and 1 do not have the Core Clock Frequency in pentium4_get_frequency()
189 rdmsr(0x2c, msr_lo, msr_hi); in pentium4_get_frequency()
191 pr_debug("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi); in pentium4_get_frequency()
198 fsb_code = (msr_lo >> 16) & 0x7; in pentium4_get_frequency()
200 case 0: in pentium4_get_frequency()
242 return 0; in speedstep_get_frequency()
244 return 0; in speedstep_get_frequency()
256 struct cpuinfo_x86 *c = &cpu_data(0); in speedstep_detect_processor()
262 ((c->x86 != 6) && (c->x86 != 0xF))) in speedstep_detect_processor()
263 return 0; in speedstep_detect_processor()
265 if (c->x86 == 0xF) { in speedstep_detect_processor()
269 return 0; in speedstep_detect_processor()
271 ebx = cpuid_ebx(0x00000001); in speedstep_detect_processor()
272 ebx &= 0x000000FF; in speedstep_detect_processor()
280 * sample has ebx = 0x0f, production has 0x0e. in speedstep_detect_processor()
282 if ((ebx == 0x0e) || (ebx == 0x0f)) in speedstep_detect_processor()
288 * needs to have ebx=0x0e, else it's a celeron: in speedstep_detect_processor()
293 if (ebx == 0x0e) in speedstep_detect_processor()
300 * this is totally strange: CPUID 0x0F29 is in speedstep_detect_processor()
304 * Celerons with CPUID 0x0F29 may have either in speedstep_detect_processor()
305 * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything in speedstep_detect_processor()
307 * M-P4-Ms may have either ebx=0xe or 0xf [see above] in speedstep_detect_processor()
308 * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf] in speedstep_detect_processor()
309 * also, M-P4M HTs have ebx=0x8, too in speedstep_detect_processor()
313 if ((ebx == 0x0e) || in speedstep_detect_processor()
321 return 0; in speedstep_detect_processor()
325 case 0x0B: /* Intel PIII [Tualatin] */ in speedstep_detect_processor()
326 /* cpuid_ebx(1) is 0x04 for desktop PIII, in speedstep_detect_processor()
327 * 0x06 for mobile PIII-M */ in speedstep_detect_processor()
328 ebx = cpuid_ebx(0x00000001); in speedstep_detect_processor()
331 ebx &= 0x000000FF; in speedstep_detect_processor()
333 if (ebx != 0x06) in speedstep_detect_processor()
334 return 0; in speedstep_detect_processor()
341 case 0x08: /* Intel PIII [Coppermine] */ in speedstep_detect_processor()
346 pr_debug("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n", in speedstep_detect_processor()
348 msr_lo &= 0x00c0000; in speedstep_detect_processor()
349 if (msr_lo != 0x0080000) in speedstep_detect_processor()
350 return 0; in speedstep_detect_processor()
359 pr_debug("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n", in speedstep_detect_processor()
363 if (c->x86_stepping == 0x01) { in speedstep_detect_processor()
371 return 0; in speedstep_detect_processor()
388 unsigned int ret = 0; in speedstep_get_freqs()