1 // SPDX-License-Identifier: GPL-2.0-only
3  *  linux/arch/arm/mach-sa1100/cpu-sa1110.c
8  *  7 - SDRAM auto-power-up failure (rev A0)
9  * 13 - Corruption of internal register reads/writes following
25 #include <asm/mach-types.h>
36 	u_char  tck;		/* clock cycle time (ns)	 */
37 	u_char  trcd;		/* activate to r/w (ns)		 */
38 	u_char  trp;		/* precharge to activate (ns)	 */
39 	u_char  twr;		/* write recovery time (ns)	 */
51 		.name		= "TC59SM716-CL2",
60 		.name		= "TC59SM716-CL3",
77 	}, {	/* Samsung K4S281632B-1H */
78 		.name           = "K4S281632B-1H",
103 	}, {	/* Micron MT48LC8M16A2TG-75 */
104 		.name		= "MT48LC8M16A2TG-75",
118  * Given a period in ns and frequency in khz, calculate the number of
122 static inline u_int ns_to_cycles(u_int ns, u_int khz)  in ns_to_cycles()  argument
124 	return (ns * khz + 999999) / 1000000;  in ns_to_cycles()
134 	rcd = 2 * rcd - 1;  in set_mdcas()
137 	mdcas[0]  = (1 << rcd) - 1;  in set_mdcas()
158 	if ((ns_to_cycles(sdram->tck, sd_khz) > 1) ||  in sdram_calculate_timing()
162 	sd->mdcnfg = MDCNFG & 0x007f007f;  in sdram_calculate_timing()
164 	twr = ns_to_cycles(sdram->twr, mem_khz);  in sdram_calculate_timing()
167 	trp = ns_to_cycles(sdram->trp, mem_khz) - 1;  in sdram_calculate_timing()
171 	sd->mdcnfg |= trp << 8;  in sdram_calculate_timing()
172 	sd->mdcnfg |= trp << 24;  in sdram_calculate_timing()
173 	sd->mdcnfg |= sdram->cas_latency << 12;  in sdram_calculate_timing()
174 	sd->mdcnfg |= sdram->cas_latency << 28;  in sdram_calculate_timing()
175 	sd->mdcnfg |= twr << 14;  in sdram_calculate_timing()
176 	sd->mdcnfg |= twr << 30;  in sdram_calculate_timing()
178 	sd->mdrefr = MDREFR & 0xffbffff0;  in sdram_calculate_timing()
179 	sd->mdrefr |= 7;  in sdram_calculate_timing()
182 		sd->mdrefr |= MDREFR_K1DB2;  in sdram_calculate_timing()
185 	set_mdcas(sd->mdcas, sd_khz >= 62000,  in sdram_calculate_timing()
186 		ns_to_cycles(sdram->trcd, mem_khz));  in sdram_calculate_timing()
190 		sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1],  in sdram_calculate_timing()
191 		sd->mdcas[2]);  in sdram_calculate_timing()
207  * always a multiple of the memory clock (fixed at cpu_clock / 2).
215 	u_int ns_row = (sdram->refresh * 1000) >> sdram->rows;  in sdram_update_refresh()
244 	if (policy->max < 147500) {  in sa1110_target()
256 	 * The clock could be going away for some time.  Set the SDRAMs  in sa1110_target()
257 	 * to refresh rapidly (every 64 memory clock cycles).  To get  in sa1110_target()
270 	 * This means that we won't access SDRAM for the duration of  in sa1110_target()
328 		if (strcmp(name, sdram->name) == 0)  in sa1110_find_sdram()
342 		return -ENODEV;  in sa1110_clk_init()
346 			name = "TC59SM716-CL3";  in sa1110_clk_init()
348 			name = "K4S281632B-1H";  in sa1110_clk_init()
355 			sdram->tck, sdram->trcd, sdram->trp,  in sa1110_clk_init()
356 			sdram->twr, sdram->refresh, sdram->cas_latency);  in sa1110_clk_init()