28 #define REG_CSCIR 0x22		/* Chip Setup and Control Index Register    */
29 #define REG_CSCDR 0x23		/* Chip Setup and Control Data  Register    */
45 	{1000,	0x02,	0x18},
46 	{2000,	0x02,	0x10},
47 	{4000,	0x02,	0x08},
48 	{8000,	0x00,	0x00},
49 	{16000,	0x00,	0x02},
50 	{33000,	0x00,	0x04},
51 	{66000,	0x01,	0x04},
52 	{99000,	0x01,	0x05}
56 	{0, 0,	1000},
57 	{0, 1,	2000},
58 	{0, 2,	4000},
59 	{0, 3,	8000},
60 	{0, 4,	16000},
61 	{0, 5,	33000},
62 	{0, 6,	66000},
63 	{0, 7,	99000},
64 	{0, 0,	CPUFREQ_TABLE_END},
82 	outb_p(0x80, REG_CSCIR);  in elanfreq_get_cpu_frequency()
86 	if ((clockspeed_reg & 0xE0) == 0xE0)  in elanfreq_get_cpu_frequency()
87 		return 0;  in elanfreq_get_cpu_frequency()
90 	if ((clockspeed_reg & 0xE0) == 0xC0) {  in elanfreq_get_cpu_frequency()
91 		if ((clockspeed_reg & 0x01) == 0)  in elanfreq_get_cpu_frequency()
98 	if ((clockspeed_reg & 0xE0) == 0xA0)  in elanfreq_get_cpu_frequency()
101 	return (1<<((clockspeed_reg & 0xE0) >> 5)) * 1000;  in elanfreq_get_cpu_frequency()
110 	 * 0x22: Chip Setup & Control Register Index Register (CSCI)  in elanfreq_target()
111 	 * 0x23: Chip Setup & Control Register Data  Register (CSCD)  in elanfreq_target()
116 	 * 0x40 is the Power Management Unit's Force Mode Register.  in elanfreq_target()
121 	outb_p(0x40, REG_CSCIR);		/* Disable hyperspeed mode */  in elanfreq_target()
122 	outb_p(0x00, REG_CSCDR);  in elanfreq_target()
128 	/* now, set the CPU clock speed register (0x80) */  in elanfreq_target()
129 	outb_p(0x80, REG_CSCIR);  in elanfreq_target()
132 	/* now, the hyperspeed bit in PMU Force Mode Register (0x40) */  in elanfreq_target()
133 	outb_p(0x40, REG_CSCIR);  in elanfreq_target()
138 	return 0;  in elanfreq_target()
146 	struct cpuinfo_x86 *c = &cpu_data(0);  in elanfreq_cpu_init()
156 		max_freq = elanfreq_get_cpu_frequency(0);  in elanfreq_cpu_init()
164 	return 0;  in elanfreq_cpu_init()
182 	max_freq = simple_strtoul(str, &str, 0);  in elanfreq_setup()