1 // SPDX-License-Identifier: GPL-2.0
3  * STM32 Timer Encoder and Counter driver
12 #include <linux/mfd/stm32-timers.h>
65 	regmap_read(priv->regmap, TIM_CNT, &cnt);  in stm32_count_read()
77 	regmap_read(priv->regmap, TIM_ARR, &ceiling);  in stm32_count_write()
79 		return -EINVAL;  in stm32_count_write()
81 	return regmap_write(priv->regmap, TIM_CNT, val);  in stm32_count_write()
91 	regmap_read(priv->regmap, TIM_SMCR, &smcr);  in stm32_count_function_read()
107 		return -EINVAL;  in stm32_count_function_read()
123 		if (!priv->has_encoder)  in stm32_count_function_write()
124 			return -EOPNOTSUPP;  in stm32_count_function_write()
128 		if (!priv->has_encoder)  in stm32_count_function_write()
129 			return -EOPNOTSUPP;  in stm32_count_function_write()
133 		if (!priv->has_encoder)  in stm32_count_function_write()
134 			return -EOPNOTSUPP;  in stm32_count_function_write()
138 		return -EINVAL;  in stm32_count_function_write()
142 	regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_count_function_write()
144 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);  in stm32_count_function_write()
146 	regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);  in stm32_count_function_write()
149 	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);  in stm32_count_function_write()
152 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1);  in stm32_count_function_write()
164 	regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_count_direction_read()
177 	regmap_read(priv->regmap, TIM_ARR, &arr);  in stm32_count_ceiling_read()
189 	if (ceiling > priv->max_arr)  in stm32_count_ceiling_write()
190 		return -ERANGE;  in stm32_count_ceiling_write()
193 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);  in stm32_count_ceiling_write()
194 	regmap_write(priv->regmap, TIM_ARR, ceiling);  in stm32_count_ceiling_write()
205 	regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_count_enable_read()
219 		regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_count_enable_write()
221 			clk_enable(priv->clk);  in stm32_count_enable_write()
223 		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,  in stm32_count_enable_write()
226 		regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_count_enable_write()
227 		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);  in stm32_count_enable_write()
229 			clk_disable(priv->clk);  in stm32_count_enable_write()
233 	priv->enabled = enable;  in stm32_count_enable_write()
244 	regmap_read(priv->regmap, TIM_PSC, &psc);  in stm32_count_prescaler_read()
258 		return -ERANGE;  in stm32_count_prescaler_write()
260 	psc = prescaler - 1;  in stm32_count_prescaler_write()
262 	return regmap_write(priv->regmap, TIM_PSC, psc);  in stm32_count_prescaler_write()
272 	if (ch >= priv->nchannels)  in stm32_count_cap_read()
273 		return -EOPNOTSUPP;  in stm32_count_cap_read()
277 		regmap_read(priv->regmap, TIM_CCR1, &ccrx);  in stm32_count_cap_read()
280 		regmap_read(priv->regmap, TIM_CCR2, &ccrx);  in stm32_count_cap_read()
283 		regmap_read(priv->regmap, TIM_CCR3, &ccrx);  in stm32_count_cap_read()
286 		regmap_read(priv->regmap, TIM_CCR4, &ccrx);  in stm32_count_cap_read()
289 		return -EINVAL;  in stm32_count_cap_read()
292 	dev_dbg(counter->parent, "CCR%zu: 0x%08x\n", ch + 1, ccrx);  in stm32_count_cap_read()
305 	spin_lock_irqsave(&priv->lock, irqflags);  in stm32_count_nb_ovf_read()
306 	*val = priv->nb_ovf;  in stm32_count_nb_ovf_read()
307 	spin_unlock_irqrestore(&priv->lock, irqflags);  in stm32_count_nb_ovf_read()
318 	spin_lock_irqsave(&priv->lock, irqflags);  in stm32_count_nb_ovf_write()
319 	priv->nb_ovf = val;  in stm32_count_nb_ovf_write()
320 	spin_unlock_irqrestore(&priv->lock, irqflags);  in stm32_count_nb_ovf_write()
362 		if (synapse->signal->id == STM32_CLOCK_SIG)  in stm32_action_read()
369 		if (synapse->signal->id == STM32_CH1_SIG)  in stm32_action_read()
376 		if (synapse->signal->id == STM32_CH2_SIG)  in stm32_action_read()
383 		if (synapse->signal->id == STM32_CH1_SIG || synapse->signal->id == STM32_CH2_SIG)  in stm32_action_read()
389 		return -EINVAL;  in stm32_action_read()
418 	if (ch >= ARRAY_SIZE(stm32_cc) || ch >= priv->nchannels) {  in stm32_count_capture_configure()
419 		dev_err(counter->parent, "invalid ch: %d\n", ch);  in stm32_count_capture_configure()
420 		return -EINVAL;  in stm32_count_capture_configure()
427 	 * Select both edges / non-inverted to trigger a capture.  in stm32_count_capture_configure()
431 		if (!regmap_test_bits(priv->regmap, TIM_CCER, cc->ccer_bits))  in stm32_count_capture_configure()
432 			regmap_write(priv->regmap, TIM_SR, ~TIM_SR_CC_IF(ch));  in stm32_count_capture_configure()
433 		regmap_update_bits(priv->regmap, cc->ccmr_reg, cc->ccmr_mask,  in stm32_count_capture_configure()
434 				   cc->ccmr_bits);  in stm32_count_capture_configure()
435 		regmap_set_bits(priv->regmap, TIM_CCER, cc->ccer_bits);  in stm32_count_capture_configure()
437 		regmap_clear_bits(priv->regmap, TIM_CCER, cc->ccer_bits);  in stm32_count_capture_configure()
438 		regmap_clear_bits(priv->regmap, cc->ccmr_reg, cc->ccmr_mask);  in stm32_count_capture_configure()
441 	regmap_read(priv->regmap, cc->ccmr_reg, &ccmr);  in stm32_count_capture_configure()
442 	regmap_read(priv->regmap, TIM_CCER, &ccer);  in stm32_count_capture_configure()
443 	dev_dbg(counter->parent, "%s(%s) ch%d 0x%08x 0x%08x\n", __func__, enable ? "ena" : "dis",  in stm32_count_capture_configure()
456 	list_for_each_entry(event_node, &counter->events_list, l) {  in stm32_count_events_configure()
457 		switch (event_node->event) {  in stm32_count_events_configure()
460 			if (!regmap_test_bits(priv->regmap, TIM_DIER, TIM_DIER_UIE))  in stm32_count_events_configure()
461 				regmap_write(priv->regmap, TIM_SR, (u32)~TIM_SR_UIF);  in stm32_count_events_configure()
465 			ret = stm32_count_capture_configure(counter, event_node->channel, true);  in stm32_count_events_configure()
468 			dier |= TIM_DIER_CCxIE(event_node->channel + 1);  in stm32_count_events_configure()
472 			return -EINVAL;  in stm32_count_events_configure()
477 	regmap_write(priv->regmap, TIM_DIER, dier);  in stm32_count_events_configure()
480 	for (i = 0 ; i < priv->nchannels; i++) {  in stm32_count_events_configure()
497 	if (!priv->nr_irqs)  in stm32_count_watch_validate()
498 		return -EOPNOTSUPP;  in stm32_count_watch_validate()
500 	switch (watch->event) {  in stm32_count_watch_validate()
502 		if (watch->channel >= priv->nchannels) {  in stm32_count_watch_validate()
503 			dev_err(counter->parent, "Invalid channel %d\n", watch->channel);  in stm32_count_watch_validate()
504 			return -EINVAL;  in stm32_count_watch_validate()
510 		return -EINVAL;  in stm32_count_watch_validate()
529 	*freq = clk_get_rate(priv->clk);  in stm32_count_clk_get_freq()
541 	 * even if they're unused or unexisting on some timer instances. It's an abstraction,
602 	.name = "STM32 Timer Counter",
619 	regmap_read(priv->regmap, TIM_SR, &sr);  in stm32_timer_cnt_isr()
620 	regmap_read(priv->regmap, TIM_DIER, &dier);  in stm32_timer_cnt_isr()
629 		spin_lock(&priv->lock);  in stm32_timer_cnt_isr()
630 		priv->nb_ovf++;  in stm32_timer_cnt_isr()
631 		spin_unlock(&priv->lock);  in stm32_timer_cnt_isr()
633 		dev_dbg(counter->parent, "COUNTER_EVENT_OVERFLOW_UNDERFLOW\n");  in stm32_timer_cnt_isr()
639 	for (i = 0 ; i < priv->nchannels; i++) {  in stm32_timer_cnt_isr()
643 			dev_dbg(counter->parent, "COUNTER_EVENT_CAPTURE, %d\n", i);  in stm32_timer_cnt_isr()
647 	regmap_write(priv->regmap, TIM_SR, clr);  in stm32_timer_cnt_isr()
657 	regmap_read(priv->regmap, TIM_CCER, &ccer_backup);  in stm32_timer_cnt_detect_channels()
658 	regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE);  in stm32_timer_cnt_detect_channels()
659 	regmap_read(priv->regmap, TIM_CCER, &ccer);  in stm32_timer_cnt_detect_channels()
660 	regmap_write(priv->regmap, TIM_CCER, ccer_backup);  in stm32_timer_cnt_detect_channels()
661 	priv->nchannels = hweight32(ccer & TIM_CCER_CCXE);  in stm32_timer_cnt_detect_channels()
663 	dev_dbg(dev, "has %d cc channels\n", priv->nchannels);  in stm32_timer_cnt_detect_channels()
670 	"st,stm32-timer-trigger",
671 	"st,stm32h7-timer-trigger",
677 	struct device *parent = dev->parent;  in stm32_timer_cnt_probe_encoder()
678 	struct device_node *tnode = NULL, *pnode = parent->of_node;  in stm32_timer_cnt_probe_encoder()
686 	 * counter modes in this driver (when the timer doesn't support  in stm32_timer_cnt_probe_encoder()
693 		return -ENODATA;  in stm32_timer_cnt_probe_encoder()
702 	priv->has_encoder = !!(STM32_TIM_ENCODER_SUPPORTED & BIT(idx));  in stm32_timer_cnt_probe_encoder()
704 	dev_dbg(dev, "encoder support: %s\n", priv->has_encoder ? "yes" : "no");  in stm32_timer_cnt_probe_encoder()
711 	struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);  in stm32_timer_cnt_probe()
712 	struct device *dev = &pdev->dev;  in stm32_timer_cnt_probe()
718 		return -EINVAL;  in stm32_timer_cnt_probe()
722 		return -ENOMEM;  in stm32_timer_cnt_probe()
726 	priv->regmap = ddata->regmap;  in stm32_timer_cnt_probe()
727 	priv->clk = ddata->clk;  in stm32_timer_cnt_probe()
728 	priv->max_arr = ddata->max_arr;  in stm32_timer_cnt_probe()
729 	priv->nr_irqs = ddata->nr_irqs;  in stm32_timer_cnt_probe()
737 	counter->name = dev_name(dev);  in stm32_timer_cnt_probe()
738 	counter->parent = dev;  in stm32_timer_cnt_probe()
739 	counter->ops = &stm32_timer_cnt_ops;  in stm32_timer_cnt_probe()
740 	counter->counts = &stm32_counts;  in stm32_timer_cnt_probe()
741 	counter->num_counts = 1;  in stm32_timer_cnt_probe()
742 	counter->signals = stm32_signals;  in stm32_timer_cnt_probe()
743 	counter->num_signals = ARRAY_SIZE(stm32_signals);  in stm32_timer_cnt_probe()
745 	spin_lock_init(&priv->lock);  in stm32_timer_cnt_probe()
749 	/* STM32 Timers can have either 1 global, or 4 dedicated interrupts (optional) */  in stm32_timer_cnt_probe()
750 	if (priv->nr_irqs == 1) {  in stm32_timer_cnt_probe()
752 		ret = devm_request_irq(&pdev->dev, ddata->irq[0], stm32_timer_cnt_isr,  in stm32_timer_cnt_probe()
756 				ddata->irq[0], ret);  in stm32_timer_cnt_probe()
760 		for (i = 0; i < priv->nr_irqs; i++) {  in stm32_timer_cnt_probe()
768 			ret = devm_request_irq(&pdev->dev, ddata->irq[i], stm32_timer_cnt_isr,  in stm32_timer_cnt_probe()
772 					ddata->irq[i], ret);  in stm32_timer_cnt_probe()
779 	regmap_write(priv->regmap, TIM_TISEL, 0x0);  in stm32_timer_cnt_probe()
794 	if (priv->enabled) {  in stm32_timer_cnt_suspend()
796 		regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);  in stm32_timer_cnt_suspend()
797 		regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);  in stm32_timer_cnt_suspend()
798 		regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);  in stm32_timer_cnt_suspend()
799 		regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);  in stm32_timer_cnt_suspend()
802 		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);  in stm32_timer_cnt_suspend()
803 		clk_disable(priv->clk);  in stm32_timer_cnt_suspend()
818 	if (priv->enabled) {  in stm32_timer_cnt_resume()
819 		clk_enable(priv->clk);  in stm32_timer_cnt_resume()
822 		regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);  in stm32_timer_cnt_resume()
823 		regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);  in stm32_timer_cnt_resume()
824 		regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);  in stm32_timer_cnt_resume()
826 		/* Also re-enables the counter */  in stm32_timer_cnt_resume()
827 		regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);  in stm32_timer_cnt_resume()
837 	{ .compatible = "st,stm32-timer-counter", },
845 		.name = "stm32-timer-counter",
853 MODULE_ALIAS("platform:stm32-timer-counter");
854 MODULE_DESCRIPTION("STMicroelectronics STM32 TIMER counter driver");