comedi/drivers/plx9080.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
26  * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
32  * Describes the format of a scatter-gather DMA descriptor for the PLX
33  * PCI 9080.  All members are raw, little-endian register values that
37  * The DMA descriptors must be aligned on a 16-byte boundary.  Bits 3:0
53 /* Local Address Space 0 Range Register */
55 /* Local Address Space 1 Range Register */
64 /* bits that specify range for memory space decode bits */
66 /* bits that specify range for i/o space decode bits */
137 /* Big Endian Byte Lane Mode - use most significant byte lanes */
154 /* Expansion ROM Range Register */
165 #define PLX_LBRD_MSWIDTH_8	(BIT(0) * 0)	/* 8 bits wide */
166 #define PLX_LBRD_MSWIDTH_16	(BIT(0) * 1)	/* 16 bits wide */
167 #define PLX_LBRD_MSWIDTH_32	(BIT(0) * 2)	/* 32 bits wide */
168 #define PLX_LBRD_MSWIDTH_32A	(BIT(0) * 3)	/* 32 bits wide */
193 #define PLX_LBRD0_EROMWIDTH_8	(BIT(16) * 0)	/* 8 bits wide */
194 #define PLX_LBRD0_EROMWIDTH_16	(BIT(16) * 1)	/* 16 bits wide */
195 #define PLX_LBRD0_EROMWIDTH_32	(BIT(16) * 2)	/* 32 bits wide */
196 #define PLX_LBRD0_EROMWIDTH_32A	(BIT(16) * 3)	/* 32 bits wide */
212 /* Direct Slave PCI Write Mode - assert TRDY# when FIFO full (LBRD0 only) */
219 /* Local Range Register for Direct Master to PCI */
243 /* Direct Master PCI Read Mode - deassert IRDY when FIFO full */
263 /* Remap of Local-to-PCI Space Into PCI Address Space */
315 /* PCI-to-Local Doorbell Register */
318 /* Local-to-PCI Doorbell Register */
330 /* Mailbox Interrupt Enable (local bus interrupts on PCI write to MBOX0-3) */
342 /* PCI Doorbell Interrupt Active (read-only) */
344 /* PCI Abort Interrupt Active (read-only) */
346 /* Local Interrupt (LINTi#) Active (read-only) */
358 /* Local Doorbell Interrupt Active (read-only) */
360 /* DMA Channel 0 Interrupt Active (read-only) */
362 /* DMA Channel 1 Interrupt Active (read-only) */
364 /* DMA Channel N Interrupt Active (N <= 1) (read-only) */
366 /* BIST Interrupt Active (read-only) */
368 /* Direct Master Not Bus Master During Master Or Target Abort (read-only) */
370 /* DMA Channel 0 Not Bus Master During Master Or Target Abort (read-only) */
372 /* DMA Channel 1 Not Bus Master During Master Or Target Abort (read-only) */
374 /* DMA Channel N Not Bus Master During Master Or Target Abort (read-only) */
377 /* Target Abort Not Generated After 256 Master Retries (read-only) */
379 /* PCI Wrote Mailbox 0 (enabled if bit 3 set) (read-only) */
381 /* PCI Wrote Mailbox 1 (enabled if bit 3 set) (read-only) */
383 /* PCI Wrote Mailbox 2 (enabled if bit 3 set) (read-only) */
385 /* PCI Wrote Mailbox 3 (enabled if bit 3 set) (read-only) */
387 /* PCI Wrote Mailbox N (N <= 3) (enabled if bit 3 set) (read-only) */
418 /* General Purpose Input (USERI) (read-only) */
426 /* Serial EEPROM Data Read Bit (EEDO (sic)) (read-only) */
428 /* Serial EEPROM Present (read-only) */
434 /* Local Init Status (read-only) */
446 /* PCI Permanent Configuration ID Register (hard-coded PLX vendor and device) */
449 /* Hard-coded ID for PLX PCI 9080 */
452 /* PCI Permanent Revision ID Register (hard-coded silicon revision) (8-bit). */
461 #define PLX_DMAMODE_WIDTH_8	(BIT(0) * 0)	/* 8 bits wide */
462 #define PLX_DMAMODE_WIDTH_16	(BIT(0) * 1)	/* 16 bits wide */
463 #define PLX_DMAMODE_WIDTH_32	(BIT(0) * 2)	/* 32 bits wide */
464 #define PLX_DMAMODE_WIDTH_32A	(BIT(0) * 3)	/* 32 bits wide */
486 /* DMA EOT Enable - enables EOT0# or EOT1# input pin */
488 /* DMA Stop Data Transfer Mode - 0:BLAST; 1:EOT asserted or DREQ deasserted */
490 /* DMA Clear Count Mode - count in descriptor cleared on completion */
492 /* DMA Channel Interrupt Select - 0:local bus interrupt; 1:PCI interrupt */
526 /* DMA Channel N Command/Status Register (N <= 1) (8-bit) */
533 /* Channel Start - write 1 to start transfer (write-only) */
535 /* Channel Abort - write 1 to abort transfer (write-only) */
537 /* Clear Interrupt - write 1 to clear DMA Channel Interrupt (write-only) */
539 /* Channel Done - transfer complete/inactive (read-only) */
553 /* DMA Channel 0 PCI-to-Local Almost Full (divided by 2, minus 1) */
557 /* DMA Channel 0 Local-to-PCI Almost Empty (divided by 2, minus 1) */
561 /* DMA Channel 0 Local-to-PCI Almost Full (divided by 2, minus 1) */
565 /* DMA Channel 0 PCI-to-Local Almost Empty (divided by 2, minus 1) */
569 /* DMA Channel 1 PCI-to-Local Almost Full (divided by 2, minus 1) */
573 /* DMA Channel 1 Local-to-PCI Almost Empty (divided by 2, minus 1) */
577 /* DMA Channel 1 Local-to-PCI Almost Full (divided by 2, minus 1) */
581 /* DMA Channel 1 PCI-to-Local Almost Empty (divided by 2, minus 1) */
597 /* Value of QSR after reset - disables I2O feature completely. */
602  * to pre-fetch data off of end-of-ram.  Limit the size of
603  * memory so host-side accesses cannot occur.
609  * plx9080_abort_dma - Abort a PLX PCI 9080 DMA transfer
618  *	-%ETIMEDOUT if timed out waiting for abort to complete.
640 		return -ETIMEDOUT;  in plx9080_abort_dma()
651 		return -ETIMEDOUT;  in plx9080_abort_dma()