comedi/drivers/plx9080.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
26  * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
32  * Describes the format of a scatter-gather DMA descriptor for the PLX
33  * PCI 9080.  All members are raw, little-endian register values that
37  * The DMA descriptors must be aligned on a 16-byte boundary.  Bits 3:0
40  * terminal count" bit, and a data transfer direction.
50  * Register Offsets and Bit Definitions
55 /* Local Address Space 1 Range Register */
58 #define PLX_LASRR_IO		BIT(0)		/* Map to: 1=I/O, 0=Mem */
59 #define PLX_LASRR_MLOC_ANY32	(BIT(1) * 0)	/* Locate anywhere in 32 bit */
60 #define PLX_LASRR_MLOC_LT1MB	(BIT(1) * 1)	/* Locate in 1st meg */
61 #define PLX_LASRR_MLOC_ANY64	(BIT(1) * 2)	/* Locate anywhere in 64 bit */
62 #define PLX_LASRR_MLOC_MASK	GENMASK(2, 1)	/* Memory location bits */
63 #define PLX_LASRR_PREFETCH	BIT(3)		/* Memory is prefetchable */
71 /* Local Address Space 1 Local Base Address (Remap) Register */
74 #define PLX_LASBA_EN		BIT(0)		/* Enable slave decode */
86 #define PLX_MARBR_LT(x)		(BIT(0) * ((x) & 0xff))
90 #define PLX_MARBR_PT(x)		(BIT(8) * ((x) & 0xff))
94 #define PLX_MARBR_LTEN		BIT(16)
96 #define PLX_MARBR_PTEN		BIT(17)
98 #define PLX_MARBR_BREQEN	BIT(18)
100 #define PLX_MARBR_PRIO_ROT	(BIT(19) * 0)	/* Rotational priority */
101 #define PLX_MARBR_PRIO_DMA0	(BIT(19) * 1)	/* DMA channel 0 has priority */
102 #define PLX_MARBR_PRIO_DMA1	(BIT(19) * 2)	/* DMA channel 1 has priority */
105 #define PLX_MARBR_DSGUBM	BIT(21)
107 #define PLX_MARBR_DSLLOCKOEN	BIT(22)
109 #define PLX_MARBR_PCIREQM	BIT(23)
110 /* PCI Specification v2.1 Mode */
111 #define PLX_MARBR_PCIV21M	BIT(24)
113 #define PLX_MARBR_PCIRNWM	BIT(25)
115 #define PLX_MARBR_PCIRWFM	BIT(26)
117 #define PLX_MARBR_GLTBREQ	BIT(27)
119 #define PLX_MARBR_PCIRNFM	BIT(28)
124 #define PLX_MARBR_SUBSYSIDS	BIT(29)
130 #define PLX_BIGEND_CONFIG	BIT(0)
132 #define PLX_BIGEND_DM		BIT(1)
134 #define PLX_BIGEND_DSAS0	BIT(2)
136 #define PLX_BIGEND_EROM		BIT(3)
137 /* Big Endian Byte Lane Mode - use most significant byte lanes */
138 #define PLX_BIGEND_BEBLM	BIT(4)
139 /* Direct Slave Address Space 1 Big Endian Mode */
140 #define PLX_BIGEND_DSAS1	BIT(5)
141 /* DMA Channel 1 Big Endian Mode */
142 #define PLX_BIGEND_DMA1		BIT(6)
144 #define PLX_BIGEND_DMA0		BIT(7)
145 /* DMA Channel N Big Endian Mode (N <= 1) */
151  *       For this reason no bit definitions are provided here.
161 /* Local Address Space 1 Bus Region Descriptor Register */
165 #define PLX_LBRD_MSWIDTH_8	(BIT(0) * 0)	/* 8 bits wide */
166 #define PLX_LBRD_MSWIDTH_16	(BIT(0) * 1)	/* 16 bits wide */
167 #define PLX_LBRD_MSWIDTH_32	(BIT(0) * 2)	/* 32 bits wide */
168 #define PLX_LBRD_MSWIDTH_32A	(BIT(0) * 3)	/* 32 bits wide */
169 #define PLX_LBRD_MSWIDTH_MASK	GENMASK(1, 0)
171 #define PLX_LBRD_MSIWS(x)	(BIT(2) * ((x) & 0xf))
175 #define PLX_LBRD_MSREADYIEN	BIT(6)
177 #define PLX_LBRD_MSBTERMIEN	BIT(7)
179 #define PLX_LBRD0_MSPREDIS	BIT(8)
180 /* Memory Space 1 Burst Enable (LBRD1 only) */
181 #define PLX_LBRD1_MSBURSTEN	BIT(8)
183 #define PLX_LBRD0_EROMPREDIS	BIT(9)
184 /* Memory Space 1 Prefetch Disable (LBRD1 only) */
185 #define PLX_LBRD1_MSPREDIS	BIT(9)
187 #define PLX_LBRD_RPFCOUNTEN	BIT(10)
189 #define PLX_LBRD_PFCOUNT(x)	(BIT(11) * ((x) & 0xf))
193 #define PLX_LBRD0_EROMWIDTH_8	(BIT(16) * 0)	/* 8 bits wide */
194 #define PLX_LBRD0_EROMWIDTH_16	(BIT(16) * 1)	/* 16 bits wide */
195 #define PLX_LBRD0_EROMWIDTH_32	(BIT(16) * 2)	/* 32 bits wide */
196 #define PLX_LBRD0_EROMWIDTH_32A	(BIT(16) * 3)	/* 32 bits wide */
199 #define PLX_LBRD0_EROMIWS(x)	(BIT(18) * ((x) & 0xf))
203 #define PLX_LBRD0_EROMREADYIEN	BIT(22)
205 #define PLX_LBRD0_EROMBTERMIEN	BIT(23)
207 #define PLX_LBRD0_MSBURSTEN	BIT(24)
209 #define PLX_LBRD0_EELONGLOAD	BIT(25)
211 #define PLX_LBRD0_EROMBURSTEN	BIT(26)
212 /* Direct Slave PCI Write Mode - assert TRDY# when FIFO full (LBRD0 only) */
213 #define PLX_LBRD0_DSWMTRDY	BIT(27)
215 #define PLX_LBRD0_TRDELAY(x)	(BIT(28) * ((x) & 0xF))
232 #define PLX_DMPBAM_MEMACCEN	BIT(0)
234 #define PLX_DMPBAM_IOACCEN	BIT(1)
236 #define PLX_DMPBAM_LLOCKIEN	BIT(2)
238 #define PLX_DMPBAM_RPSIZE_CONT	((BIT(12) * 0) | (BIT(3) * 0))
239 #define PLX_DMPBAM_RPSIZE_4	((BIT(12) * 0) | (BIT(3) * 1))
240 #define PLX_DMPBAM_RPSIZE_8	((BIT(12) * 1) | (BIT(3) * 0))
241 #define PLX_DMPBAM_RPSIZE_16	((BIT(12) * 1) | (BIT(3) * 1))
242 #define PLX_DMPBAM_RPSIZE_MASK	(BIT(12) | BIT(3))
243 /* Direct Master PCI Read Mode - deassert IRDY when FIFO full */
244 #define PLX_DMPBAM_RMIRDY	BIT(4)
246 #define PLX_DMPBAM_PAFL(x)	((BIT(10) * !!((x) & 0x10)) | \
247 				 (BIT(5) * ((x) & 0xf)))
248 #define PLX_DMPBAM_TO_PAFL(v)	((((BIT(10) & (v)) >> 1) | \
250 #define PLX_DMPBAM_PAFL_MASK	(BIT(10) | GENMASK(8, 5))
252 #define PLX_DMPBAM_WIM		BIT(9)
254 #define PLX_DBPBAM_PFLIMIT	BIT(11)
256 #define PLX_DMPBAM_IOREMAPSEL	BIT(13)
258 #define PLX_DMPBAM_WDELAY_NONE	(BIT(14) * 0)
259 #define PLX_DMPBAM_WDELAY_4	(BIT(14) * 1)
260 #define PLX_DMPBAM_WDELAY_8	(BIT(14) * 2)
261 #define PLX_DMPBAM_WDELAY_16	(BIT(14) * 3)
263 /* Remap of Local-to-PCI Space Into PCI Address Space */
270 #define PLX_DMCFGA_TYPE0	(BIT(0) * 0)
271 #define PLX_DMCFGA_TYPE1	(BIT(0) * 1)
272 #define PLX_DMCFGA_TYPE_MASK	GENMASK(1, 0)
274 #define PLX_DMCFGA_REGNUM(x)	(BIT(2) * ((x) & 0x3f))
278 #define PLX_DMCFGA_FUNCNUM(x)	(BIT(8) * ((x) & 0x7))
282 #define PLX_DMCFGA_DEVNUM(x)	(BIT(11) * ((x) & 0x1f))
286 #define PLX_DMCFGA_BUSNUM(x)	(BIT(16) * ((x) & 0xff))
290 #define PLX_DMCFGA_CONFIGEN	BIT(31)
296  * is replaced by the Inbound Queue Port, and Mailbox Register 1 is replaced
297  * by the Outbound Queue Port.  However, Mailbox Register 0 and 1 are always
302 #define PLX_REG_MBOX1		PLX_REG_MBOX(1)
310 /* Alternative offsets for Mailbox Registers 0 and 1 (in case I2O is enabled) */
313 #define PLX_REG_ALT_MBOX1	PLX_REG_ALT_MBOX(1)
315 /* PCI-to-Local Doorbell Register */
318 /* Local-to-PCI Doorbell Register */
325 #define PLX_INTCSR_LSEABORTEN	BIT(0)
327 #define PLX_INTCSR_LSEPARITYEN	BIT(1)
328 /* Generate PCI Bus SERR# when set to 1 */
329 #define PLX_INTCSR_GENSERR	BIT(2)
330 /* Mailbox Interrupt Enable (local bus interrupts on PCI write to MBOX0-3) */
331 #define PLX_INTCSR_MBIEN	BIT(3)
333 #define PLX_INTCSR_PIEN		BIT(8)
335 #define PLX_INTCSR_PDBIEN	BIT(9)
337 #define PLX_INTCSR_PABORTIEN	BIT(10)
339 #define PLX_INTCSR_PLIEN	BIT(11)
341 #define PLX_INTCSR_RAEN		BIT(12)
342 /* PCI Doorbell Interrupt Active (read-only) */
343 #define PLX_INTCSR_PDBIA	BIT(13)
344 /* PCI Abort Interrupt Active (read-only) */
345 #define PLX_INTCSR_PABORTIA	BIT(14)
346 /* Local Interrupt (LINTi#) Active (read-only) */
347 #define PLX_INTCSR_PLIA		BIT(15)
349 #define PLX_INTCSR_LIOEN	BIT(16)
351 #define PLX_INTCSR_LDBIEN	BIT(17)
353 #define PLX_INTCSR_DMA0IEN	BIT(18)
354 /* DMA Channel 1 Interrupt Enable */
355 #define PLX_INTCSR_DMA1IEN	BIT(19)
356 /* DMA Channel N Interrupt Enable (N <= 1) */
358 /* Local Doorbell Interrupt Active (read-only) */
359 #define PLX_INTCSR_LDBIA	BIT(20)
360 /* DMA Channel 0 Interrupt Active (read-only) */
361 #define PLX_INTCSR_DMA0IA	BIT(21)
362 /* DMA Channel 1 Interrupt Active (read-only) */
363 #define PLX_INTCSR_DMA1IA	BIT(22)
364 /* DMA Channel N Interrupt Active (N <= 1) (read-only) */
366 /* BIST Interrupt Active (read-only) */
367 #define PLX_INTCSR_BISTIA	BIT(23)
368 /* Direct Master Not Bus Master During Master Or Target Abort (read-only) */
369 #define PLX_INTCSR_ABNOTDM	BIT(24)
370 /* DMA Channel 0 Not Bus Master During Master Or Target Abort (read-only) */
371 #define PLX_INTCSR_ABNOTDMA0	BIT(25)
372 /* DMA Channel 1 Not Bus Master During Master Or Target Abort (read-only) */
373 #define PLX_INTCSR_ABNOTDMA1	BIT(26)
374 /* DMA Channel N Not Bus Master During Master Or Target Abort (read-only) */
377 /* Target Abort Not Generated After 256 Master Retries (read-only) */
378 #define PLX_INTCSR_ABNOTRETRY	BIT(27)
379 /* PCI Wrote Mailbox 0 (enabled if bit 3 set) (read-only) */
380 #define PLX_INTCSR_MB0IA	BIT(28)
381 /* PCI Wrote Mailbox 1 (enabled if bit 3 set) (read-only) */
382 #define PLX_INTCSR_MB1IA	BIT(29)
383 /* PCI Wrote Mailbox 2 (enabled if bit 3 set) (read-only) */
384 #define PLX_INTCSR_MB2IA	BIT(30)
385 /* PCI Wrote Mailbox 3 (enabled if bit 3 set) (read-only) */
386 #define PLX_INTCSR_MB3IA	BIT(31)
387 /* PCI Wrote Mailbox N (N <= 3) (enabled if bit 3 set) (read-only) */
388 #define PLX_INTCSR_MBIA(n)	BIT(28 + (n))
397 #define PLX_CNTRL_CCRDMA(x)	(BIT(0) * ((x) & 0xf))
402 #define PLX_CNTRL_CCWDMA(x)	(BIT(4) * ((x) & 0xf))
407 #define PLX_CNTRL_CCRDM(x)	(BIT(8) * ((x) & 0xf))
412 #define PLX_CNTRL_CCWDM(x)	(BIT(12) * ((x) & 0xf))
417 #define PLX_CNTRL_USERO		BIT(16)
418 /* General Purpose Input (USERI) (read-only) */
419 #define PLX_CNTRL_USERI		BIT(17)
421 #define PLX_CNTRL_EESK		BIT(24)
423 #define PLX_CNTRL_EECS		BIT(25)
424 /* Serial EEPROM Data Write Bit (EEDI (sic)) */
425 #define PLX_CNTRL_EEWB		BIT(26)
426 /* Serial EEPROM Data Read Bit (EEDO (sic)) (read-only) */
427 #define PLX_CNTRL_EERB		BIT(27)
428 /* Serial EEPROM Present (read-only) */
429 #define PLX_CNTRL_EEPRESENT	BIT(28)
431 #define PLX_CNTRL_EERELOAD	BIT(29)
433 #define PLX_CNTRL_RESET		BIT(30)
434 /* Local Init Status (read-only) */
435 #define PLX_CNTRL_INITDONE	BIT(31)
446 /* PCI Permanent Configuration ID Register (hard-coded PLX vendor and device) */
449 /* Hard-coded ID for PLX PCI 9080 */
452 /* PCI Permanent Revision ID Register (hard-coded silicon revision) (8-bit). */
455 /* DMA Channel N Mode Register (N <= 1) */
461 #define PLX_DMAMODE_WIDTH_8	(BIT(0) * 0)	/* 8 bits wide */
462 #define PLX_DMAMODE_WIDTH_16	(BIT(0) * 1)	/* 16 bits wide */
463 #define PLX_DMAMODE_WIDTH_32	(BIT(0) * 2)	/* 32 bits wide */
464 #define PLX_DMAMODE_WIDTH_32A	(BIT(0) * 3)	/* 32 bits wide */
465 #define PLX_DMAMODE_WIDTH_MASK	GENMASK(1, 0)
467 #define PLX_DMAMODE_IWS(x)	(BIT(2) * ((x) & 0xf))
471 #define PLX_DMAMODE_READYIEN	BIT(6)
473 #define PLX_DMAMODE_BTERMIEN	BIT(7)
475 #define PLX_DMAMODE_BURSTEN	BIT(8)
477 #define PLX_DMAMODE_CHAINEN	BIT(9)
479 #define PLX_DMAMODE_DONEIEN	BIT(10)
481 #define PLX_DMAMODE_LACONST	BIT(11)
483 #define PLX_DMAMODE_DEMAND	BIT(12)
485 #define PLX_DMAMODE_WINVALIDATE	BIT(13)
486 /* DMA EOT Enable - enables EOT0# or EOT1# input pin */
487 #define PLX_DMAMODE_EOTEN	BIT(14)
488 /* DMA Stop Data Transfer Mode - 0:BLAST; 1:EOT asserted or DREQ deasserted */
489 #define PLX_DMAMODE_STOP	BIT(15)
490 /* DMA Clear Count Mode - count in descriptor cleared on completion */
491 #define PLX_DMAMODE_CLRCOUNT	BIT(16)
492 /* DMA Channel Interrupt Select - 0:local bus interrupt; 1:PCI interrupt */
493 #define PLX_DMAMODE_INTRPCI	BIT(17)
495 /* DMA Channel N PCI Address Register (N <= 1) */
500 /* DMA Channel N Local Address Register (N <= 1) */
505 /* DMA Channel N Transfer Size (Bytes) Register (N <= 1) (first 23 bits) */
510 /* DMA Channel N Descriptor Pointer Register (N <= 1) */
516 #define PLX_DMADPR_DESCPCI	BIT(0)
518 #define PLX_DMADPR_CHAINEND	BIT(1)
520 #define PLX_DMADPR_TCINTR	BIT(2)
522 #define PLX_DMADPR_XFERL2P	BIT(3)
526 /* DMA Channel N Command/Status Register (N <= 1) (8-bit) */
532 #define PLX_DMACSR_ENABLE	BIT(0)
533 /* Channel Start - write 1 to start transfer (write-only) */
534 #define PLX_DMACSR_START	BIT(1)
535 /* Channel Abort - write 1 to abort transfer (write-only) */
536 #define PLX_DMACSR_ABORT	BIT(2)
537 /* Clear Interrupt - write 1 to clear DMA Channel Interrupt (write-only) */
538 #define PLX_DMACSR_CLEARINTR	BIT(3)
539 /* Channel Done - transfer complete/inactive (read-only) */
540 #define PLX_DMACSR_DONE		BIT(4)
547  * (C0PLAF + 1) + (C0PLAE + 1) <= 32
548  * (C0LPAF + 1) + (C0LPAE + 1) <= 32
549  * (C1PLAF + 1) + (C1PLAE + 1) <= 16
550  * (C1LPAF + 1) + (C1LPAE + 1) <= 16
553 /* DMA Channel 0 PCI-to-Local Almost Full (divided by 2, minus 1) */
554 #define PLX_DMATHR_C0PLAF(x)	(BIT(0) * ((x) & 0xf))
557 /* DMA Channel 0 Local-to-PCI Almost Empty (divided by 2, minus 1) */
558 #define PLX_DMATHR_C0LPAE(x)	(BIT(4) * ((x) & 0xf))
561 /* DMA Channel 0 Local-to-PCI Almost Full (divided by 2, minus 1) */
562 #define PLX_DMATHR_C0LPAF(x)	(BIT(8) * ((x) & 0xf))
565 /* DMA Channel 0 PCI-to-Local Almost Empty (divided by 2, minus 1) */
566 #define PLX_DMATHR_C0PLAE(x)	(BIT(12) * ((x) & 0xf))
569 /* DMA Channel 1 PCI-to-Local Almost Full (divided by 2, minus 1) */
570 #define PLX_DMATHR_C1PLAF(x)	(BIT(16) * ((x) & 0xf))
573 /* DMA Channel 1 Local-to-PCI Almost Empty (divided by 2, minus 1) */
574 #define PLX_DMATHR_C1LPAE(x)	(BIT(20) * ((x) & 0xf))
577 /* DMA Channel 1 Local-to-PCI Almost Full (divided by 2, minus 1) */
578 #define PLX_DMATHR_C1LPAF(x)	(BIT(24) * ((x) & 0xf))
581 /* DMA Channel 1 PCI-to-Local Almost Empty (divided by 2, minus 1) */
582 #define PLX_DMATHR_C1PLAE(x)	(BIT(28) * ((x) & 0xf))
597 /* Value of QSR after reset - disables I2O feature completely. */
602  * to pre-fetch data off of end-of-ram.  Limit the size of
603  * memory so host-side accesses cannot occur.
609  * plx9080_abort_dma - Abort a PLX PCI 9080 DMA transfer
611  * @channel:	DMA channel number (0 or 1).
618  *	-%ETIMEDOUT if timed out waiting for abort to complete.
634 	/* wait to make sure done bit is zero */  in plx9080_abort_dma()
636 		udelay(1);  in plx9080_abort_dma()
640 		return -ETIMEDOUT;  in plx9080_abort_dma()
644 	/* wait for dma done bit */  in plx9080_abort_dma()
647 		udelay(1);  in plx9080_abort_dma()
651 		return -ETIMEDOUT;  in plx9080_abort_dma()