1 // SPDX-License-Identifier: GPL-2.0+
15 #include <linux/clk/clk-conf.h>
17 #include <clocksource/timer-ti-dm.h>
18 #include <dt-bindings/bus/ti-sysc.h>
34  * Subset of the timer registers we use. Note that the register offsets
35  * depend on the timer revision detected.
68 	u32 tidr = readl_relaxed(t->base);  in dmtimer_systimer_revision1()
82 	writel_relaxed(val, t->base + t->sysc);  in dmtimer_systimer_enable()
90 	writel_relaxed(DMTIMER_TYPE1_DISABLE, t->base + t->sysc);  in dmtimer_systimer_disable()
95 	void __iomem *syss = t->base + OMAP_TIMER_V1_SYS_STAT_OFFSET;  in dmtimer_systimer_type1_reset()
100 	writel_relaxed(BIT(1) | BIT(2), t->base + t->ifctrl);  in dmtimer_systimer_type1_reset()
110 	void __iomem *sysc = t->base + t->sysc;  in dmtimer_systimer_type2_reset()
140 	{ .compatible = "ti,omap-counter32k" },
146  * counter is handled by timer-ti-32k, but we need to detect it as it
147  * affects the preferred dmtimer system timer configuration. There is
160 		counter_32k = -ENODEV;  in dmtimer_systimer_check_counter32k()
168 		counter_32k = -ENODEV;  in dmtimer_systimer_check_counter32k()
174 	{ .compatible = "ti,omap2420-timer", },
175 	{ .compatible = "ti,omap3430-timer", },
176 	{ .compatible = "ti,omap4430-timer", },
177 	{ .compatible = "ti,omap5430-timer", },
178 	{ .compatible = "ti,am335x-timer", },
179 	{ .compatible = "ti,am335x-timer-1ms", },
180 	{ .compatible = "ti,dm814-timer", },
181 	{ .compatible = "ti,dm816-timer", },
187  * the generic timer-ti-dm device driver probe. And that the system timer
196 	if (!of_property_read_bool(np->parent,  in dmtimer_is_preferred()
197 				   "ti,no-reset-on-init"))  in dmtimer_is_preferred()
200 	if (!of_property_read_bool(np->parent, "ti,no-idle"))  in dmtimer_is_preferred()
204 	if (!of_property_read_bool(np, "ti,timer-secure")) {  in dmtimer_is_preferred()
205 		if (!of_property_read_bool(np, "assigned-clocks"))  in dmtimer_is_preferred()
208 		if (!of_property_read_bool(np, "assigned-clock-parents"))  in dmtimer_is_preferred()
212 	if (of_property_read_bool(np, "ti,timer-dsp"))  in dmtimer_is_preferred()
215 	if (of_property_read_bool(np, "ti,timer-pwm"))  in dmtimer_is_preferred()
222  * Finds the first available usable always-on timer, and assigns it to either
229  * ti,always-on property, but let's not count on it. For these quirky cases,
230  * we prefer using the always-on secure dmtimer12 with the internal 32 KiHz
244 	if (of_machine_is_compatible("ti,omap3-beagle-ab4")) {  in dmtimer_systimer_assign_alwon()
246 		counter_32k = -ENODEV;  in dmtimer_systimer_assign_alwon()
251 		counter_32k = -ENODEV;  in dmtimer_systimer_assign_alwon()
258 		if (!of_property_read_bool(np, "ti,timer-alwon"))  in dmtimer_systimer_assign_alwon()
336 	if ((PTR_ERR(clock) == -EINVAL) && is_ick)  in dmtimer_systimer_init_clock()
348 		return -ENODEV;  in dmtimer_systimer_init_clock()
352 		t->ick = clock;  in dmtimer_systimer_init_clock()
354 		t->fck = clock;  in dmtimer_systimer_init_clock()
368 	if (!of_device_is_compatible(np->parent, "ti,sysc"))  in dmtimer_systimer_setup()
369 		return -EINVAL;  in dmtimer_systimer_setup()
371 	t->base = of_iomap(np, 0);  in dmtimer_systimer_setup()
372 	if (!t->base)  in dmtimer_systimer_setup()
373 		return -ENXIO;  in dmtimer_systimer_setup()
376 	 * Enable optional assigned-clock-parents configured at the timer  in dmtimer_systimer_setup()
384 	/* For ti-sysc, we have timer clocks at the parent module level */  in dmtimer_systimer_setup()
385 	error = dmtimer_systimer_init_clock(t, np->parent, "fck", &rate);  in dmtimer_systimer_setup()
389 	t->rate = rate;  in dmtimer_systimer_setup()
391 	error = dmtimer_systimer_init_clock(t, np->parent, "ick", &rate);  in dmtimer_systimer_setup()
396 		t->irq_stat = OMAP_TIMER_V1_STAT_OFFSET;  in dmtimer_systimer_setup()
397 		t->irq_ena = OMAP_TIMER_V1_INT_EN_OFFSET;  in dmtimer_systimer_setup()
398 		t->pend = _OMAP_TIMER_WRITE_PEND_OFFSET;  in dmtimer_systimer_setup()
401 		t->irq_stat = OMAP_TIMER_V2_IRQSTATUS;  in dmtimer_systimer_setup()
402 		t->irq_ena = OMAP_TIMER_V2_IRQENABLE_SET;  in dmtimer_systimer_setup()
404 		t->pend = regbase + _OMAP_TIMER_WRITE_PEND_OFFSET;  in dmtimer_systimer_setup()
407 	t->sysc = OMAP_TIMER_OCP_CFG_OFFSET;  in dmtimer_systimer_setup()
408 	t->load = regbase + _OMAP_TIMER_LOAD_OFFSET;  in dmtimer_systimer_setup()
409 	t->counter = regbase + _OMAP_TIMER_COUNTER_OFFSET;  in dmtimer_systimer_setup()
410 	t->ctrl = regbase + _OMAP_TIMER_CTRL_OFFSET;  in dmtimer_systimer_setup()
411 	t->wakeup = regbase + _OMAP_TIMER_WAKEUP_EN_OFFSET;  in dmtimer_systimer_setup()
412 	t->ifctrl = regbase + _OMAP_TIMER_IF_CTRL_OFFSET;  in dmtimer_systimer_setup()
416 	pr_debug("dmtimer rev %08x sysc %08x\n", readl_relaxed(t->base),  in dmtimer_systimer_setup()
417 		 readl_relaxed(t->base + t->sysc));  in dmtimer_systimer_setup()
422 	iounmap(t->base);  in dmtimer_systimer_setup()
437 	struct dmtimer_systimer *t = &clkevt->t;  in dmtimer_clockevent_interrupt()
439 	writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat);  in dmtimer_clockevent_interrupt()
440 	clkevt->dev.event_handler(&clkevt->dev);  in dmtimer_clockevent_interrupt()
449 	struct dmtimer_systimer *t = &clkevt->t;  in dmtimer_set_next_event()
450 	void __iomem *pend = t->base + t->pend;  in dmtimer_set_next_event()
454 	writel_relaxed(0xffffffff - cycles, t->base + t->counter);  in dmtimer_set_next_event()
458 	writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl);  in dmtimer_set_next_event()
466 	struct dmtimer_systimer *t = &clkevt->t;  in dmtimer_clockevent_shutdown()
467 	void __iomem *ctrl = t->base + t->ctrl;  in dmtimer_clockevent_shutdown()
477 		udelay(3500000 / t->rate + 1);  in dmtimer_clockevent_shutdown()
479 	writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat);  in dmtimer_clockevent_shutdown()
487 	struct dmtimer_systimer *t = &clkevt->t;  in dmtimer_set_periodic()
488 	void __iomem *pend = t->base + t->pend;  in dmtimer_set_periodic()
495 	writel_relaxed(clkevt->period, t->base + t->load);  in dmtimer_set_periodic()
499 	writel_relaxed(clkevt->period, t->base + t->counter);  in dmtimer_set_periodic()
504 		       t->base + t->ctrl);  in dmtimer_set_periodic()
512 	struct dmtimer_systimer *t = &clkevt->t;  in omap_clockevent_idle()
515 	clk_disable(t->fck);  in omap_clockevent_idle()
521 	struct dmtimer_systimer *t = &clkevt->t;  in omap_clockevent_unidle()
524 	error = clk_enable(t->fck);  in omap_clockevent_unidle()
526 		pr_err("could not enable timer fck on resume: %i\n", error);  in omap_clockevent_unidle()
529 	writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena);  in omap_clockevent_unidle()
530 	writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);  in omap_clockevent_unidle()
544 	t = &clkevt->t;  in dmtimer_clkevt_init_common()
545 	dev = &clkevt->dev;  in dmtimer_clkevt_init_common()
551 	dev->features = features;  in dmtimer_clkevt_init_common()
552 	dev->rating = rating;  in dmtimer_clkevt_init_common()
553 	dev->set_next_event = dmtimer_set_next_event;  in dmtimer_clkevt_init_common()
554 	dev->set_state_shutdown = dmtimer_clockevent_shutdown;  in dmtimer_clkevt_init_common()
555 	dev->set_state_periodic = dmtimer_set_periodic;  in dmtimer_clkevt_init_common()
556 	dev->set_state_oneshot = dmtimer_clockevent_shutdown;  in dmtimer_clkevt_init_common()
557 	dev->set_state_oneshot_stopped = dmtimer_clockevent_shutdown;  in dmtimer_clkevt_init_common()
558 	dev->tick_resume = dmtimer_clockevent_shutdown;  in dmtimer_clkevt_init_common()
559 	dev->cpumask = cpumask;  in dmtimer_clkevt_init_common()
561 	dev->irq = irq_of_parse_and_map(np, 0);  in dmtimer_clkevt_init_common()
562 	if (!dev->irq)  in dmtimer_clkevt_init_common()
563 		return -ENXIO;  in dmtimer_clkevt_init_common()
565 	error = dmtimer_systimer_setup(np, &clkevt->t);  in dmtimer_clkevt_init_common()
569 	clkevt->period = 0xffffffff - DIV_ROUND_CLOSEST(t->rate, HZ);  in dmtimer_clkevt_init_common()
572 	 * For clock-event timers we never read the timer counter and  in dmtimer_clkevt_init_common()
574 	 * we can safely ignore this errata for clock-event timers.  in dmtimer_clkevt_init_common()
576 	writel_relaxed(OMAP_TIMER_CTRL_POSTED, t->base + t->ifctrl);  in dmtimer_clkevt_init_common()
578 	error = request_irq(dev->irq, dmtimer_clockevent_interrupt,  in dmtimer_clkevt_init_common()
583 	writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena);  in dmtimer_clkevt_init_common()
584 	writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);  in dmtimer_clkevt_init_common()
587 		name, of_property_read_bool(np, "ti,timer-alwon") ?  in dmtimer_clkevt_init_common()
588 		"always-on " : "", t->rate, np->parent);  in dmtimer_clkevt_init_common()
593 	iounmap(t->base);  in dmtimer_clkevt_init_common()
605 		return -ENOMEM;  in dmtimer_clockevent_init()
615 	clockevents_config_and_register(&clkevt->dev, clkevt->t.rate,  in dmtimer_clockevent_init()
616 					3, /* Timer internal resync latency */  in dmtimer_clockevent_init()
621 		clkevt->dev.suspend = omap_clockevent_idle;  in dmtimer_clockevent_init()
622 		clkevt->dev.resume = omap_clockevent_unidle;  in dmtimer_clockevent_init()
633 /* Dmtimer as percpu timer. See dra7 ARM architected timer wrap erratum i940 */
642 		return -EINVAL;  in dmtimer_percpu_timer_init()
644 	if (!of_property_read_bool(np->parent, "ti,no-reset-on-init") ||  in dmtimer_percpu_timer_init()
645 	    !of_property_read_bool(np->parent, "ti,no-idle"))  in dmtimer_percpu_timer_init()
646 		pr_warn("Incomplete dtb for percpu dmtimer %pOF\n", np->parent);  in dmtimer_percpu_timer_init()
651 					   cpumask_of(cpu), "percpu-dmtimer",  in dmtimer_percpu_timer_init()
659 /* See TRM for timer internal resynch latency */
663 	struct clock_event_device *dev = &clkevt->dev;  in omap_dmtimer_starting_cpu()
664 	struct dmtimer_systimer *t = &clkevt->t;  in omap_dmtimer_starting_cpu()
666 	clockevents_config_and_register(dev, t->rate, 3, ULONG_MAX);  in omap_dmtimer_starting_cpu()
667 	irq_force_affinity(dev->irq, cpumask_of(cpu));  in omap_dmtimer_starting_cpu()
675 	struct dmtimer_systimer *t = &clkevt->t;  in dmtimer_percpu_timer_startup()
677 	if (t->sysc) {  in dmtimer_percpu_timer_startup()
691 	arm_timer = of_find_compatible_node(NULL, NULL, "arm,armv7-timer");  in dmtimer_percpu_quirk_init()
693 		pr_warn_once("ARM architected timer wrap issue i940 detected\n");  in dmtimer_percpu_quirk_init()
715 	struct dmtimer_systimer *t = &clksrc->t;  in dmtimer_clocksource_read_cycles()
717 	return (u64)readl_relaxed(t->base + t->counter);  in dmtimer_clocksource_read_cycles()
730 	struct dmtimer_systimer *t = &clksrc->t;  in dmtimer_clocksource_suspend()
732 	clksrc->loadval = readl_relaxed(t->base + t->counter);  in dmtimer_clocksource_suspend()
734 	clk_disable(t->fck);  in dmtimer_clocksource_suspend()
740 	struct dmtimer_systimer *t = &clksrc->t;  in dmtimer_clocksource_resume()
743 	error = clk_enable(t->fck);  in dmtimer_clocksource_resume()
745 		pr_err("could not enable timer fck on resume: %i\n", error);  in dmtimer_clocksource_resume()
748 	writel_relaxed(clksrc->loadval, t->base + t->counter);  in dmtimer_clocksource_resume()
750 		       t->base + t->ctrl);  in dmtimer_clocksource_resume()
762 		return -ENOMEM;  in dmtimer_clocksource_init()
764 	dev = &clksrc->dev;  in dmtimer_clocksource_init()
765 	t = &clksrc->t;  in dmtimer_clocksource_init()
771 	dev->name = "dmtimer";  in dmtimer_clocksource_init()
772 	dev->rating = 300;  in dmtimer_clocksource_init()
773 	dev->read = dmtimer_clocksource_read_cycles;  in dmtimer_clocksource_init()
774 	dev->mask = CLOCKSOURCE_MASK(32);  in dmtimer_clocksource_init()
775 	dev->flags = CLOCK_SOURCE_IS_CONTINUOUS;  in dmtimer_clocksource_init()
779 		dev->suspend = dmtimer_clocksource_suspend;  in dmtimer_clocksource_init()
780 		dev->resume = dmtimer_clocksource_resume;  in dmtimer_clocksource_init()
783 	writel_relaxed(0, t->base + t->counter);  in dmtimer_clocksource_init()
785 		       t->base + t->ctrl);  in dmtimer_clocksource_init()
788 		of_property_read_bool(np, "ti,timer-alwon") ?  in dmtimer_clocksource_init()
789 		"always-on " : "", np->parent);  in dmtimer_clocksource_init()
792 		dmtimer_sched_clock_counter = t->base + t->counter;  in dmtimer_clocksource_init()
793 		sched_clock_register(dmtimer_read_sched_clock, 32, t->rate);  in dmtimer_clocksource_init()
796 	if (clocksource_register_hz(dev, t->rate))  in dmtimer_clocksource_init()
804 	return -ENODEV;  in dmtimer_clocksource_init()
809  * has no interrupts configured for a clocksource timer.
816 	/* One time init for the preferred timer configuration */  in dmtimer_systimer_init()
824 		return -EINVAL;  in dmtimer_systimer_init()
831 		return -EINVAL;  in dmtimer_systimer_init()
845 TIMER_OF_DECLARE(systimer_omap2, "ti,omap2420-timer", dmtimer_systimer_init);
846 TIMER_OF_DECLARE(systimer_omap3, "ti,omap3430-timer", dmtimer_systimer_init);
847 TIMER_OF_DECLARE(systimer_omap4, "ti,omap4430-timer", dmtimer_systimer_init);
848 TIMER_OF_DECLARE(systimer_omap5, "ti,omap5430-timer", dmtimer_systimer_init);
849 TIMER_OF_DECLARE(systimer_am33x, "ti,am335x-timer", dmtimer_systimer_init);
850 TIMER_OF_DECLARE(systimer_am3ms, "ti,am335x-timer-1ms", dmtimer_systimer_init);
851 TIMER_OF_DECLARE(systimer_dm814, "ti,dm814-timer", dmtimer_systimer_init);
852 TIMER_OF_DECLARE(systimer_dm816, "ti,dm816-timer", dmtimer_systimer_init);