1 // SPDX-License-Identifier: GPL-2.0-only
9 #define pr_fmt(fmt)	"tegra-timer: " fmt
24 #include "timer-of.h"
60 	 * Tegra's timer uses n+1 scheme for the counter, i.e. timer will  in tegra_timer_set_next_event()
68 	writel_relaxed(TIMER_PTV_EN | (cycles - 1), reg_base + TIMER_PTV);  in tegra_timer_set_next_event()
87 	writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1),  in tegra_timer_set_periodic()
99 	evt->event_handler(evt);  in tegra_timer_isr()
139 	irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));  in tegra_timer_setup()
140 	enable_irq(to->clkevt.irq);  in tegra_timer_setup()
143 	 * Tegra's timer uses n+1 scheme for the counter, i.e. timer will  in tegra_timer_setup()
150 	clockevents_config_and_register(&to->clkevt, timer_of_rate(to),  in tegra_timer_setup()
161 	to->clkevt.set_state_shutdown(&to->clkevt);  in tegra_timer_stop()
162 	disable_irq_nosync(to->clkevt.irq);  in tegra_timer_stop()
189  * tegra_rtc_read - Reads the Tegra RTC registers
212 static inline unsigned int tegra_base_for_cpu(int cpu, bool tegra20)  in tegra_base_for_cpu()  argument
214 	if (tegra20) {  in tegra_base_for_cpu()
230 static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20)  in tegra_irq_idx_for_cpu()  argument
232 	if (tegra20)  in tegra_irq_idx_for_cpu()
239 						 bool tegra20)  in tegra_rate_for_timer()  argument
242 	 * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the  in tegra_rate_for_timer()
245 	if (tegra20)  in tegra_rate_for_timer()
251 static int __init tegra_init_timer(struct device_node *np, bool tegra20,  in tegra_init_timer()  argument
295 		ret = -EINVAL;  in tegra_init_timer()
304 		unsigned long rate = tegra_rate_for_timer(to, tegra20);  in tegra_init_timer()
305 		unsigned int base = tegra_base_for_cpu(cpu, tegra20);  in tegra_init_timer()
306 		unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20);  in tegra_init_timer()
311 			ret = -EINVAL;  in tegra_init_timer()
315 		cpu_to->clkevt.irq = irq;  in tegra_init_timer()
316 		cpu_to->clkevt.rating = rating;  in tegra_init_timer()
317 		cpu_to->clkevt.cpumask = cpumask_of(cpu);  in tegra_init_timer()
318 		cpu_to->of_base.base = timer_reg_base + base;  in tegra_init_timer()
319 		cpu_to->of_clk.period = rate / HZ;  in tegra_init_timer()
320 		cpu_to->of_clk.rate = rate;  in tegra_init_timer()
322 		irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);  in tegra_init_timer()
324 		ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr, flags,  in tegra_init_timer()
325 				  cpu_to->clkevt.name, &cpu_to->clkevt);  in tegra_init_timer()
329 			irq_dispose_mapping(cpu_to->clkevt.irq);  in tegra_init_timer()
330 			cpu_to->clkevt.irq = 0;  in tegra_init_timer()
360 		if (cpu_to->clkevt.irq) {  in tegra_init_timer()
361 			free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);  in tegra_init_timer()
362 			irq_dispose_mapping(cpu_to->clkevt.irq);  in tegra_init_timer()
366 	to->of_base.base = timer_reg_base;  in tegra_init_timer()
376 	 * Arch-timer can't survive across power cycle of CPU core and  in tegra210_init_timer()
378 	 * hence tegra-timer is more preferable on Tegra210.  in tegra210_init_timer()
382 TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer);
389 	 * Tegra20 and Tegra30 have Cortex A9 CPU that has a TWD timer,  in tegra20_init_timer()
390 	 * that timer runs off the CPU clock and hence is subjected to  in tegra20_init_timer()
391 	 * a jitter caused by DVFS clock rate changes. Tegra-timer is  in tegra20_init_timer()
393 	 * have arch-timer as a main per-CPU timer and it is not affected  in tegra20_init_timer()
396 	if (of_machine_is_compatible("nvidia,tegra20") ||  in tegra20_init_timer()
404 TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
416 TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);