1 // SPDX-License-Identifier: GPL-2.0
3  * 64-bit Periodic Interval Timer driver
10 #include <linux/clk.h>
12 #include <linux/delay.h>
51  * struct mchp_pit64b_timer - PIT64B timer data structure
59 	struct clk	*pclk;
60 	struct clk	*gclk;
65  * struct mchp_pit64b_clkevt - PIT64B clockevent data structure
79  * struct mchp_pit64b_clksrc - PIT64B clocksource data structure
94 /* Default cycles for clockevent timer. */
96 /* Delay timer. */
120 				     u64 cycles, u32 mode, u32 irqs)  in mchp_pit64b_reset()  argument
124 	low = cycles & MCHP_PIT64B_LSBMASK;  in mchp_pit64b_reset()
125 	high = cycles >> 32;  in mchp_pit64b_reset()
127 	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);  in mchp_pit64b_reset()
128 	writel_relaxed(mode | timer->mode, timer->base + MCHP_PIT64B_MR);  in mchp_pit64b_reset()
129 	writel_relaxed(high, timer->base + MCHP_PIT64B_MSB_PR);  in mchp_pit64b_reset()
130 	writel_relaxed(low, timer->base + MCHP_PIT64B_LSB_PR);  in mchp_pit64b_reset()
131 	writel_relaxed(irqs, timer->base + MCHP_PIT64B_IER);  in mchp_pit64b_reset()
132 	writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR);  in mchp_pit64b_reset()
137 	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);  in mchp_pit64b_suspend()
138 	if (timer->mode & MCHP_PIT64B_MR_SGCLK)  in mchp_pit64b_suspend()
139 		clk_disable_unprepare(timer->gclk);  in mchp_pit64b_suspend()
140 	clk_disable_unprepare(timer->pclk);  in mchp_pit64b_suspend()
145 	clk_prepare_enable(timer->pclk);  in mchp_pit64b_resume()
146 	if (timer->mode & MCHP_PIT64B_MR_SGCLK)  in mchp_pit64b_resume()
147 		clk_prepare_enable(timer->gclk);  in mchp_pit64b_resume()
232 	readl_relaxed(irq_data->timer.base + MCHP_PIT64B_ISR);  in mchp_pit64b_interrupt()
234 	irq_data->clkevt.event_handler(&irq_data->clkevt);  in mchp_pit64b_interrupt()
252 		*pres = MCHP_PIT64B_PRES_MAX - 1;  in mchp_pit64b_pres_compute()
256  * mchp_pit64b_init_mode() - prepare PIT64B mode register value to be used at
276  *  PMC             +------------------------------------+
277  * +----+           |   +-----+                          |
278  * |    |-->gclk -->|-->|     |    +---------+  +-----+  |
279  * |    |           |   | MUX |--->| Divider |->|timer|  |
280  * |    |-->pclk -->|-->|     |    +---------+  +-----+  |
281  * +----+           |   +-----+                          |
284  *                  +------------------------------------+
287  *	- gclk rate <= pclk rate/3
288  *	- gclk rate could be requested from PMC
289  *	- pclk rate is fixed (cannot be requested from PMC)
298 	pclk_rate = clk_get_rate(timer->pclk);  in mchp_pit64b_init_mode()
300 		return -EINVAL;  in mchp_pit64b_init_mode()
302 	timer->mode = 0;  in mchp_pit64b_init_mode()
305 	gclk_round = clk_round_rate(timer->gclk, max_rate);  in mchp_pit64b_init_mode()
313 	best_diff = abs(gclk_round / (pres + 1) - max_rate);  in mchp_pit64b_init_mode()
317 		timer->mode |= MCHP_PIT64B_MR_SGCLK;  in mchp_pit64b_init_mode()
318 		clk_set_rate(timer->gclk, gclk_round);  in mchp_pit64b_init_mode()
325 	diff = abs(pclk_rate / (pres + 1) - max_rate);  in mchp_pit64b_init_mode()
332 		timer->mode |= MCHP_PIT64B_MR_SGCLK;  in mchp_pit64b_init_mode()
333 		clk_set_rate(timer->gclk, gclk_round);  in mchp_pit64b_init_mode()
337 	timer->mode |= MCHP_PIT64B_PRES_TO_MODE(best_pres);  in mchp_pit64b_init_mode()
339 	pr_info("PIT64B: using clk=%s with prescaler %u, freq=%lu [Hz]\n",  in mchp_pit64b_init_mode()
340 		timer->mode & MCHP_PIT64B_MR_SGCLK ? "gclk" : "pclk", best_pres,  in mchp_pit64b_init_mode()
341 		timer->mode & MCHP_PIT64B_MR_SGCLK ?  in mchp_pit64b_init_mode()
355 		return -ENOMEM;  in mchp_pit64b_init_clksrc()
360 	mchp_pit64b_cs_base = timer->base;  in mchp_pit64b_init_clksrc()
362 	cs->timer.base = timer->base;  in mchp_pit64b_init_clksrc()
363 	cs->timer.pclk = timer->pclk;  in mchp_pit64b_init_clksrc()
364 	cs->timer.gclk = timer->gclk;  in mchp_pit64b_init_clksrc()
365 	cs->timer.mode = timer->mode;  in mchp_pit64b_init_clksrc()
366 	cs->clksrc.name = MCHP_PIT64B_NAME;  in mchp_pit64b_init_clksrc()
367 	cs->clksrc.mask = CLOCKSOURCE_MASK(64);  in mchp_pit64b_init_clksrc()
368 	cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;  in mchp_pit64b_init_clksrc()
369 	cs->clksrc.rating = 210;  in mchp_pit64b_init_clksrc()
370 	cs->clksrc.read = mchp_pit64b_clksrc_read;  in mchp_pit64b_init_clksrc()
371 	cs->clksrc.suspend = mchp_pit64b_clksrc_suspend;  in mchp_pit64b_init_clksrc()
372 	cs->clksrc.resume = mchp_pit64b_clksrc_resume;  in mchp_pit64b_init_clksrc()
374 	ret = clocksource_register_hz(&cs->clksrc, clk_rate);  in mchp_pit64b_init_clksrc()
402 		return -ENOMEM;  in mchp_pit64b_init_clkevt()
406 	ce->timer.base = timer->base;  in mchp_pit64b_init_clkevt()
407 	ce->timer.pclk = timer->pclk;  in mchp_pit64b_init_clkevt()
408 	ce->timer.gclk = timer->gclk;  in mchp_pit64b_init_clkevt()
409 	ce->timer.mode = timer->mode;  in mchp_pit64b_init_clkevt()
410 	ce->clkevt.name = MCHP_PIT64B_NAME;  in mchp_pit64b_init_clkevt()
411 	ce->clkevt.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC;  in mchp_pit64b_init_clkevt()
412 	ce->clkevt.rating = 150;  in mchp_pit64b_init_clkevt()
413 	ce->clkevt.set_state_shutdown = mchp_pit64b_clkevt_shutdown;  in mchp_pit64b_init_clkevt()
414 	ce->clkevt.set_state_periodic = mchp_pit64b_clkevt_set_periodic;  in mchp_pit64b_init_clkevt()
415 	ce->clkevt.set_state_oneshot = mchp_pit64b_clkevt_set_oneshot;  in mchp_pit64b_init_clkevt()
416 	ce->clkevt.set_next_event = mchp_pit64b_clkevt_set_next_event;  in mchp_pit64b_init_clkevt()
417 	ce->clkevt.cpumask = cpumask_of(0);  in mchp_pit64b_init_clkevt()
418 	ce->clkevt.irq = irq;  in mchp_pit64b_init_clkevt()
428 	clockevents_config_and_register(&ce->clkevt, clk_rate, 1, ULONG_MAX);  in mchp_pit64b_init_clkevt()
452 		return -ENXIO;  in mchp_pit64b_dt_init_timer()
457 			ret = -ENODEV;  in mchp_pit64b_dt_init_timer()
505 	return -EINVAL;  in mchp_pit64b_dt_init()
508 TIMER_OF_DECLARE(mchp_pit64b, "microchip,sam9x60-pit64b", mchp_pit64b_dt_init);