1 // SPDX-License-Identifier: GPL-2.0+
3 //  Copyright (C) 2000-2001 Deep Blue Solutions
5 //  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
22  *  - MX1/MXL
23  *  - MX21, MX27.
24  *  - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
25  *  - MX6DL, MX6SX, MX6Q(rev1.1+)
73 	const struct imx_gpt_data *gpt;  member
98 	tmp = readl_relaxed(imxtm->base + MXC_TCTL);  in imx1_gpt_irq_disable()
99 	writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);  in imx1_gpt_irq_disable()
104 	writel_relaxed(0, imxtm->base + V2_IR);  in imx31_gpt_irq_disable()
111 	tmp = readl_relaxed(imxtm->base + MXC_TCTL);  in imx1_gpt_irq_enable()
112 	writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);  in imx1_gpt_irq_enable()
117 	writel_relaxed(1<<0, imxtm->base + V2_IR);  in imx31_gpt_irq_enable()
122 	writel_relaxed(0, imxtm->base + MX1_2_TSTAT);  in imx1_gpt_irq_acknowledge()
128 				imxtm->base + MX1_2_TSTAT);  in imx21_gpt_irq_acknowledge()
133 	writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT);  in imx31_gpt_irq_acknowledge()
154 	unsigned int c = clk_get_rate(imxtm->clk_per);  in mxc_clocksource_init()
155 	void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn;  in mxc_clocksource_init()
178 	tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt;  in mx1_2_set_next_event()
180 	writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP);  in mx1_2_set_next_event()
182 	return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ?  in mx1_2_set_next_event()
183 				-ETIME : 0;  in mx1_2_set_next_event()
192 	tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt;  in v2_set_next_event()
194 	writel_relaxed(tcmp, imxtm->base + V2_TCMP);  in v2_set_next_event()
197 		(int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ?  in v2_set_next_event()
198 				-ETIME : 0;  in v2_set_next_event()
206 	/* Disable interrupt in GPT module */  in mxc_shutdown()
207 	imxtm->gpt->gpt_irq_disable(imxtm);  in mxc_shutdown()
209 	tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);  in mxc_shutdown()
210 	/* Set event time into far-far future */  in mxc_shutdown()
211 	writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);  in mxc_shutdown()
214 	imxtm->gpt->gpt_irq_acknowledge(imxtm);  in mxc_shutdown()
227 	/* Disable interrupt in GPT module */  in mxc_set_oneshot()
228 	imxtm->gpt->gpt_irq_disable(imxtm);  in mxc_set_oneshot()
231 		u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);  in mxc_set_oneshot()
232 		/* Set event time into far-far future */  in mxc_set_oneshot()
233 		writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);  in mxc_set_oneshot()
236 		imxtm->gpt->gpt_irq_acknowledge(imxtm);  in mxc_set_oneshot()
249 	imxtm->gpt->gpt_irq_enable(imxtm);  in mxc_set_oneshot()
262 	readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat);  in mxc_timer_interrupt()
264 	imxtm->gpt->gpt_irq_acknowledge(imxtm);  in mxc_timer_interrupt()
266 	ced->event_handler(ced);  in mxc_timer_interrupt()
273 	struct clock_event_device *ced = &imxtm->ced;  in mxc_clockevent_init()
275 	ced->name = "mxc_timer1";  in mxc_clockevent_init()
276 	ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;  in mxc_clockevent_init()
277 	ced->set_state_shutdown = mxc_shutdown;  in mxc_clockevent_init()
278 	ced->set_state_oneshot = mxc_set_oneshot;  in mxc_clockevent_init()
279 	ced->tick_resume = mxc_shutdown;  in mxc_clockevent_init()
280 	ced->set_next_event = imxtm->gpt->set_next_event;  in mxc_clockevent_init()
281 	ced->rating = 200;  in mxc_clockevent_init()
282 	ced->cpumask = cpumask_of(0);  in mxc_clockevent_init()
283 	ced->irq = imxtm->irq;  in mxc_clockevent_init()
284 	clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per),  in mxc_clockevent_init()
287 	return request_irq(imxtm->irq, mxc_timer_interrupt,  in mxc_clockevent_init()
296 	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);  in imx1_gpt_setup_tctl()
304 	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8)  in imx31_gpt_setup_tctl()
309 	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);  in imx31_gpt_setup_tctl()
317 	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) {  in imx6dl_gpt_setup_tctl()
320 		writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);  in imx6dl_gpt_setup_tctl()
326 	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);  in imx6dl_gpt_setup_tctl()
377 	switch (imxtm->type) {  in _mxc_timer_init()
379 		imxtm->gpt = &imx1_gpt_data;  in _mxc_timer_init()
382 		imxtm->gpt = &imx21_gpt_data;  in _mxc_timer_init()
385 		imxtm->gpt = &imx31_gpt_data;  in _mxc_timer_init()
388 		imxtm->gpt = &imx6dl_gpt_data;  in _mxc_timer_init()
391 		return -EINVAL;  in _mxc_timer_init()
394 	if (IS_ERR(imxtm->clk_per)) {  in _mxc_timer_init()
396 		return PTR_ERR(imxtm->clk_per);  in _mxc_timer_init()
399 	if (!IS_ERR(imxtm->clk_ipg))  in _mxc_timer_init()
400 		clk_prepare_enable(imxtm->clk_ipg);  in _mxc_timer_init()
402 	clk_prepare_enable(imxtm->clk_per);  in _mxc_timer_init()
408 	writel_relaxed(0, imxtm->base + MXC_TCTL);  in _mxc_timer_init()
409 	writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */  in _mxc_timer_init()
411 	imxtm->gpt->gpt_setup_tctl(imxtm);  in _mxc_timer_init()
433 		return -ENOMEM;  in mxc_timer_init_dt()
435 	imxtm->base = of_iomap(np, 0);  in mxc_timer_init_dt()
436 	if (!imxtm->base) {  in mxc_timer_init_dt()
437 		ret = -ENXIO;  in mxc_timer_init_dt()
441 	imxtm->irq = irq_of_parse_and_map(np, 0);  in mxc_timer_init_dt()
442 	if (imxtm->irq <= 0) {  in mxc_timer_init_dt()
443 		ret = -EINVAL;  in mxc_timer_init_dt()
447 	imxtm->clk_ipg = of_clk_get_by_name(np, "ipg");  in mxc_timer_init_dt()
450 	imxtm->clk_per = of_clk_get_by_name(np, "osc_per");  in mxc_timer_init_dt()
451 	if (IS_ERR(imxtm->clk_per))  in mxc_timer_init_dt()
452 		imxtm->clk_per = of_clk_get_by_name(np, "per");  in mxc_timer_init_dt()
454 	imxtm->type = type;  in mxc_timer_init_dt()
485 	 * GPT device, while they actually have different programming model.  in imx31_timer_init_dt()
500 TIMER_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
501 TIMER_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
502 TIMER_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt);
503 TIMER_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
504 TIMER_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
505 TIMER_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
506 TIMER_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
507 TIMER_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
508 TIMER_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
509 TIMER_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
510 TIMER_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
511 TIMER_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);