drivers/clocksource/timer-ep93xx.c

1 // SPDX-License-Identifier: GPL-2.0
6  * Based on a rewrite of arch/arm/mach-ep93xx/timer.c:
14 #include <linux/io-64-nonatomic-lo-hi.h>
26  * The ep93xx has four internal timers.  Timers 1, 2 (both 16 bit) and
27  * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
28  * an interrupt on underflow.  Timer 4 (40 bit) counts down at 983.04 kHz,
29  * is free-running, and can't generate interrupts.
32  * most common values of HZ divide 508 kHz nicely.  We pick the 32 bit
38  * a stable 40 bit time base.
45 #define EP93XX_TIMER123_CONTROL_ENABLE	BIT(7)
46 #define EP93XX_TIMER123_CONTROL_MODE	BIT(6)
47 #define EP93XX_TIMER123_CONTROL_CLKSEL	BIT(3)
54  * This read-only register contains the low word of the time stamp debug timer
60 #define EP93XX_TIMER4_VALUE_HIGH_ENABLE	BIT(8)
79 	return lo_hi_readq(tcu->base + EP93XX_TIMER4_VALUE_LOW) & GENMASK_ULL(39, 0);  in ep93xx_clocksource_read()
96 	writel(tmode, tcu->base + EP93XX_TIMER3_CONTROL);  in ep93xx_clkevt_set_next_event()
99 	writel(next, tcu->base + EP93XX_TIMER3_LOAD);  in ep93xx_clkevt_set_next_event()
101 	       tcu->base + EP93XX_TIMER3_CONTROL);  in ep93xx_clkevt_set_next_event()
109 	writel(0, tcu->base + EP93XX_TIMER3_CONTROL);  in ep93xx_clkevt_shutdown()
130 	writel(1, tcu->base + EP93XX_TIMER3_CLEAR);  in ep93xx_timer_interrupt()
132 	evt->event_handler(evt);  in ep93xx_timer_interrupt()
146 		return -ENOMEM;  in ep93xx_timer_of_init()
148 	tcu->base = of_iomap(np, 0);  in ep93xx_timer_of_init()
149 	if (!tcu->base) {  in ep93xx_timer_of_init()
151 		ret = -ENXIO;  in ep93xx_timer_of_init()
159 		ret = -EINVAL;  in ep93xx_timer_of_init()
166 	       tcu->base + EP93XX_TIMER4_VALUE_HIGH);  in ep93xx_timer_of_init()
168 				EP93XX_TIMER4_RATE, 200, 40,  in ep93xx_timer_of_init()
170 	sched_clock_register(ep93xx_read_sched_clock, 40,  in ep93xx_timer_of_init()
189 TIMER_OF_DECLARE(ep93xx_timer, "cirrus,ep9301-timer", ep93xx_timer_of_init);