1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
51 	writel_relaxed(val, to_mps2_clkevt(c)->reg + offset);  in clockevent_mps2_writel()
72 	u32 clock_count_per_tick = to_mps2_clkevt(ce)->clock_count_per_tick;  in mps2_timer_set_periodic()
84 	u32 status = readl_relaxed(ce->reg + TIMER_INT);  in mps2_timer_interrupt()
91 	writel_relaxed(1, ce->reg + TIMER_INT);  in mps2_timer_interrupt()
93 	ce->clkevt.event_handler(&ce->clkevt);  in mps2_timer_interrupt()
101 	struct clk *clk = NULL;  in mps2_clockevent_init()  local
105 	const char *name = "mps2-clkevt";  in mps2_clockevent_init()
107 	ret = of_property_read_u32(np, "clock-frequency", &rate);  in mps2_clockevent_init()
109 		clk = of_clk_get(np, 0);  in mps2_clockevent_init()
110 		if (IS_ERR(clk)) {  in mps2_clockevent_init()
111 			ret = PTR_ERR(clk);  in mps2_clockevent_init()
113 			goto out;  in mps2_clockevent_init()
116 		ret = clk_prepare_enable(clk);  in mps2_clockevent_init()
122 		rate = clk_get_rate(clk);  in mps2_clockevent_init()
127 		ret = -EADDRNOTAVAIL;  in mps2_clockevent_init()
134 		ret = -ENOENT;  in mps2_clockevent_init()
141 		ret = -ENOMEM;  in mps2_clockevent_init()
145 	ce->reg = base;  in mps2_clockevent_init()
146 	ce->clock_count_per_tick = DIV_ROUND_CLOSEST(rate, HZ);  in mps2_clockevent_init()
147 	ce->clkevt.irq = irq;  in mps2_clockevent_init()
148 	ce->clkevt.name = name;  in mps2_clockevent_init()
149 	ce->clkevt.rating = 200;  in mps2_clockevent_init()
150 	ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;  in mps2_clockevent_init()
151 	ce->clkevt.cpumask = cpu_possible_mask;  in mps2_clockevent_init()
152 	ce->clkevt.set_state_shutdown	= mps2_timer_shutdown;  in mps2_clockevent_init()
153 	ce->clkevt.set_state_periodic	= mps2_timer_set_periodic;  in mps2_clockevent_init()
154 	ce->clkevt.set_state_oneshot	= mps2_timer_shutdown;  in mps2_clockevent_init()
155 	ce->clkevt.set_next_event	= mps2_timer_set_next_event;  in mps2_clockevent_init()
166 	clockevents_config_and_register(&ce->clkevt, rate, 0xf, 0xffffffff);  in mps2_clockevent_init()
176 	clk_disable_unprepare(clk);  in mps2_clockevent_init()
178 	clk_put(clk);  in mps2_clockevent_init()
179 out:  in mps2_clockevent_init()
186 	struct clk *clk = NULL;  in mps2_clocksource_init()  local
189 	const char *name = "mps2-clksrc";  in mps2_clocksource_init()
191 	ret = of_property_read_u32(np, "clock-frequency", &rate);  in mps2_clocksource_init()
193 		clk = of_clk_get(np, 0);  in mps2_clocksource_init()
194 		if (IS_ERR(clk)) {  in mps2_clocksource_init()
195 			ret = PTR_ERR(clk);  in mps2_clocksource_init()
197 			goto out;  in mps2_clocksource_init()
200 		ret = clk_prepare_enable(clk);  in mps2_clocksource_init()
206 		rate = clk_get_rate(clk);  in mps2_clocksource_init()
211 		ret = -EADDRNOTAVAIL;  in mps2_clocksource_init()
219 	/* ... and set it up as free-running clocksource */  in mps2_clocksource_init()
242 	clk_disable_unprepare(clk);  in mps2_clocksource_init()
244 	clk_put(clk);  in mps2_clocksource_init()
245 out:  in mps2_clocksource_init()
273 TIMER_OF_DECLARE(mps2_timer, "arm,mps2-timer", mps2_timer_init);