51 static void __iomem *gt_base;  variable
72 	upper = readl_relaxed(gt_base + GT_COUNTER1);  in _gt_counter_read()
75 		lower = readl_relaxed(gt_base + GT_COUNTER0);  in _gt_counter_read()
76 		upper = readl_relaxed(gt_base + GT_COUNTER1);  in _gt_counter_read()
104 	ctrl = readl(gt_base + GT_CONTROL);  in gt_compare_set()
108 	writel_relaxed(ctrl, gt_base + GT_CONTROL);  in gt_compare_set()
109 	writel_relaxed(lower_32_bits(counter), gt_base + GT_COMP0);  in gt_compare_set()
110 	writel_relaxed(upper_32_bits(counter), gt_base + GT_COMP1);  in gt_compare_set()
113 		writel_relaxed(delta, gt_base + GT_AUTO_INC);  in gt_compare_set()
118 	writel_relaxed(ctrl, gt_base + GT_CONTROL);  in gt_compare_set()
125 	ctrl = readl(gt_base + GT_CONTROL);  in gt_clockevent_shutdown()
128 	writel(ctrl, gt_base + GT_CONTROL);  in gt_clockevent_shutdown()
149 	if (!(readl_relaxed(gt_base + GT_INT_STATUS) &  in gt_clockevent_interrupt()
167 	writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);  in gt_clockevent_interrupt()
212 	ctrl = readl(gt_base + GT_CONTROL);  in gt_resume()
215 		writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);  in gt_resume()
236 	return readl_relaxed(gt_base + GT_COUNTER0);  in gt_read_long()
247 	reg = readl(gt_base + GT_CONTROL);  in gt_write_presc()
250 	writel(reg, gt_base + GT_CONTROL);  in gt_write_presc()
257 	reg = readl(gt_base + GT_CONTROL);  in gt_read_presc()
269 	writel(0, gt_base + GT_CONTROL);  in gt_clocksource_init()
270 	writel(0, gt_base + GT_COUNTER0);  in gt_clocksource_init()
271 	writel(0, gt_base + GT_COUNTER1);  in gt_clocksource_init()
275 	       GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);  in gt_clocksource_init()
365 	gt_base = of_iomap(np, 0);  in global_timer_of_register()
366 	if (!gt_base) {  in global_timer_of_register()
431 	iounmap(gt_base);  in global_timer_of_register()