1 // SPDX-License-Identifier: GPL-2.0
5  *  Copyright (C) 2016-2018 Xilinx
9 #include <linux/clk-provider.h>
11 #include "clk-zynqmp.h"
14  * struct zynqmp_pll - PLL clock
15  * @hw:		Handle between common and hardware-specific interfaces
44  * zynqmp_pll_get_mode() - Get mode of PLL
45  * @hw:		Handle between common and hardware-specific interfaces
47  * Return: Mode of PLL
52 	u32 clk_id = clk->clk_id;  in zynqmp_pll_get_mode()
59 		pr_debug("%s() PLL get frac mode failed for %s, ret = %d\n",  in zynqmp_pll_get_mode()
68  * zynqmp_pll_set_mode() - Set the PLL mode
69  * @hw:		Handle between common and hardware-specific interfaces
70  * @on:		Flag to determine the mode
75 	u32 clk_id = clk->clk_id;  in zynqmp_pll_set_mode()
78 	u32 mode;  in zynqmp_pll_set_mode()  local
81 		mode = PLL_MODE_FRAC;  in zynqmp_pll_set_mode()
83 		mode = PLL_MODE_INT;  in zynqmp_pll_set_mode()
85 	ret = zynqmp_pm_set_pll_frac_mode(clk_id, mode);  in zynqmp_pll_set_mode()
87 		pr_debug("%s() PLL set frac mode failed for %s, ret = %d\n",  in zynqmp_pll_set_mode()
90 		clk->set_pll_mode = true;  in zynqmp_pll_set_mode()
94  * zynqmp_pll_round_rate() - Round a clock frequency
95  * @hw:		Handle between common and hardware-specific interfaces
127  * zynqmp_pll_recalc_rate() - Recalculate clock frequency
128  * @hw:			Handle between common and hardware-specific interfaces
137 	u32 clk_id = clk->clk_id;  in zynqmp_pll_recalc_rate()
143 	enum pll_mode mode;  in zynqmp_pll_recalc_rate()  local
147 		pr_debug("%s() get divider failed for %s, ret = %d\n",  in zynqmp_pll_recalc_rate()
152 	mode = zynqmp_pll_get_mode(hw);  in zynqmp_pll_recalc_rate()
153 	if (mode == PLL_MODE_ERROR)  in zynqmp_pll_recalc_rate()
157 	if (mode == PLL_MODE_FRAC) {  in zynqmp_pll_recalc_rate()
168  * zynqmp_pll_set_rate() - Set rate of PLL
169  * @hw:			Handle between common and hardware-specific interfaces
181 	u32 clk_id = clk->clk_id;  in zynqmp_pll_set_rate()
198 		if (ret == -EUSERS)  in zynqmp_pll_set_rate()
199 			WARN(1, "More than allowed devices are using the %s, which is forbidden\n",  in zynqmp_pll_set_rate()
202 			pr_debug("%s() set divider failed for %s, ret = %d\n",  in zynqmp_pll_set_rate()
213 		pr_debug("%s() set divider failed for %s, ret = %d\n",  in zynqmp_pll_set_rate()
220  * zynqmp_pll_is_enabled() - Check if a clock is enabled
221  * @hw:		Handle between common and hardware-specific interfaces
229 	u32 clk_id = clk->clk_id;  in zynqmp_pll_is_enabled()
235 		pr_debug("%s() clock get state failed for %s, ret = %d\n",  in zynqmp_pll_is_enabled()
237 		return -EIO;  in zynqmp_pll_is_enabled()
244  * zynqmp_pll_enable() - Enable clock
245  * @hw:		Handle between common and hardware-specific interfaces
253 	u32 clk_id = clk->clk_id;  in zynqmp_pll_enable()
260 	if (zynqmp_pll_is_enabled(hw) && (!clk->set_pll_mode))  in zynqmp_pll_enable()
263 	clk->set_pll_mode = false;  in zynqmp_pll_enable()
267 		pr_debug("%s() clock enable failed for %s, ret = %d\n",  in zynqmp_pll_enable()
274  * zynqmp_pll_disable() - Disable clock
275  * @hw:		Handle between common and hardware-specific interfaces
281 	u32 clk_id = clk->clk_id;  in zynqmp_pll_disable()
289 		pr_debug("%s() clock disable failed for %s, ret = %d\n",  in zynqmp_pll_disable()
303  * zynqmp_clk_register_pll() - Register PLL with the clock framework
306  * @parents:		Name of this clock's parents
325 	init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);  in zynqmp_clk_register_pll()
332 		return ERR_PTR(-ENOMEM);  in zynqmp_clk_register_pll()
334 	pll->hw.init = &init;  in zynqmp_clk_register_pll()
335 	pll->clk_id = clk_id;  in zynqmp_clk_register_pll()
337 	hw = &pll->hw;  in zynqmp_clk_register_pll()