1 // SPDX-License-Identifier: GPL-2.0
5  *  Copyright (C) 2016-2019 Xilinx
11 #include <linux/clk-provider.h>
13 #include "clk-zynqmp.h"
19  * prepare - clk_prepare only ensures that parents are prepared
20  * enable - clk_enable only ensures that parents are enabled
21  * rate - rate is adjustable.  clk->rate = ceiling(parent->rate / divisor)
22  * parent - fixed parent.  No clk_set_parent support
28 #define CLK_FRAC		BIT(13) /* has a fractional parent */
29 #define CUSTOM_FLAG_CLK_FRAC	BIT(0) /* has a fractional parent in custom type flag */
32  * struct zynqmp_clk_divider - adjustable divider clock
33  * @hw:		handle between common and hardware-specific interfaces
50 					 unsigned long rate, u16 flags)  in zynqmp_divider_get_val()  argument
56 		up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);  in zynqmp_divider_get_val()
57 		down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate);  in zynqmp_divider_get_val()
65 		return (rate - up_rate) <= (down_rate - rate) ? up : down;  in zynqmp_divider_get_val()
68 		return DIV_ROUND_CLOSEST(parent_rate, rate);  in zynqmp_divider_get_val()
73  * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
74  * @hw:			handle between common and hardware-specific interfaces
75  * @parent_rate:	rate of parent clock
84 	u32 clk_id = divider->clk_id;  in zynqmp_clk_divider_recalc_rate()
85 	u32 div_type = divider->div_type;  in zynqmp_clk_divider_recalc_rate()
100 	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_clk_divider_recalc_rate()
104 		WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),  in zynqmp_clk_divider_recalc_rate()
114  * zynqmp_clk_divider_round_rate() - Round rate of divider clock
115  * @hw:			handle between common and hardware-specific interfaces
116  * @rate:		rate of clock to be set
117  * @prate:		rate of parent clock
122 					  unsigned long rate,  in zynqmp_clk_divider_round_rate()  argument
127 	u32 clk_id = divider->clk_id;  in zynqmp_clk_divider_round_rate()
128 	u32 div_type = divider->div_type;  in zynqmp_clk_divider_round_rate()
134 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in zynqmp_clk_divider_round_rate()
145 		if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_clk_divider_round_rate()
151 	width = fls(divider->max_div);  in zynqmp_clk_divider_round_rate()
153 	rate = divider_round_rate(hw, rate, prate, NULL, width, divider->flags);  in zynqmp_clk_divider_round_rate()
155 	if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (rate % *prate))  in zynqmp_clk_divider_round_rate()
156 		*prate = rate;  in zynqmp_clk_divider_round_rate()
158 	return rate;  in zynqmp_clk_divider_round_rate()
162  * zynqmp_clk_divider_set_rate() - Set rate of divider clock
163  * @hw:			handle between common and hardware-specific interfaces
164  * @rate:		rate of clock to be set
165  * @parent_rate:	rate of parent clock
169 static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,  in zynqmp_clk_divider_set_rate()  argument
174 	u32 clk_id = divider->clk_id;  in zynqmp_clk_divider_set_rate()
175 	u32 div_type = divider->div_type;  in zynqmp_clk_divider_set_rate()
179 	value = zynqmp_divider_get_val(parent_rate, rate, divider->flags);  in zynqmp_clk_divider_set_rate()
188 	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_clk_divider_set_rate()
212  * zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware.
263  * zynqmp_clk_register_divider() - Register a divider clock
286 		return ERR_PTR(-ENOMEM);  in zynqmp_clk_register_divider()
289 	if (nodes->type_flag & CLK_DIVIDER_READ_ONLY)  in zynqmp_clk_register_divider()
294 	init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);  in zynqmp_clk_register_divider()
300 	div->is_frac = !!((nodes->flag & CLK_FRAC) |  in zynqmp_clk_register_divider()
301 			  (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC));  in zynqmp_clk_register_divider()
302 	div->flags = zynqmp_clk_map_divider_ccf_flags(nodes->type_flag);  in zynqmp_clk_register_divider()
303 	div->hw.init = &init;  in zynqmp_clk_register_divider()
304 	div->clk_id = clk_id;  in zynqmp_clk_register_divider()
305 	div->div_type = nodes->type;  in zynqmp_clk_register_divider()
308 	 * To achieve best possible rate, maximum limit of divider is required  in zynqmp_clk_register_divider()
311 	div->max_div = zynqmp_clk_get_max_divisor(clk_id, nodes->type);  in zynqmp_clk_register_divider()
313 	hw = &div->hw;  in zynqmp_clk_register_divider()