21  * rate - rate is adjustable.  clk->rate = ceiling(parent->rate / divisor)
50 					 unsigned long rate, u16 flags)  in zynqmp_divider_get_val()  argument
56 		up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);  in zynqmp_divider_get_val()
57 		down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate);  in zynqmp_divider_get_val()
65 		return (rate - up_rate) <= (down_rate - rate) ? up : down;  in zynqmp_divider_get_val()
68 		return DIV_ROUND_CLOSEST(parent_rate, rate);  in zynqmp_divider_get_val()
73  * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
75  * @parent_rate:	rate of parent clock
114  * zynqmp_clk_divider_round_rate() - Round rate of divider clock
116  * @rate:		rate of clock to be set
117  * @prate:		rate of parent clock
122 					  unsigned long rate,  in zynqmp_clk_divider_round_rate()  argument
153 	rate = divider_round_rate(hw, rate, prate, NULL, width, divider->flags);  in zynqmp_clk_divider_round_rate()
155 	if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (rate % *prate))  in zynqmp_clk_divider_round_rate()
156 		*prate = rate;  in zynqmp_clk_divider_round_rate()
158 	return rate;  in zynqmp_clk_divider_round_rate()
162  * zynqmp_clk_divider_set_rate() - Set rate of divider clock
164  * @rate:		rate of clock to be set
165  * @parent_rate:	rate of parent clock
169 static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,  in zynqmp_clk_divider_set_rate()  argument
179 	value = zynqmp_divider_get_val(parent_rate, rate, divider->flags);  in zynqmp_clk_divider_set_rate()
308 	 * To achieve best possible rate, maximum limit of divider is required  in zynqmp_clk_register_divider()