1 // SPDX-License-Identifier: GPL-2.0
5  *  Copyright (C) 2016-2019 Xilinx
12 #include <linux/clk-provider.h>
19 #include "clk-zynqmp.h"
49  * struct clock_parent - Clock parent
61  * struct zynqmp_clock - Clock
89 #define CLK_TOPOLOGY_FLAGS		GENMASK(23, 8)
141  * zynqmp_is_valid_clock() - Check whether clock is valid or not
149 		return -ENODEV;  in zynqmp_is_valid_clock()
155  * zynqmp_get_clock_name() - Get name of clock from Clock index
171 	return ret == 0 ? -EINVAL : ret;  in zynqmp_get_clock_name()
175  * zynqmp_get_clock_type() - Get type of clock
191 	return ret == 0 ? -EINVAL : ret;  in zynqmp_get_clock_type()
195  * zynqmp_pm_clock_get_num_clocks() - Get number of clocks in system
217  * zynqmp_pm_clock_get_name() - Get the name of clock for given id
246  * zynqmp_pm_clock_get_topology() - Get the topology of clock for given id
300  * zynqmp_clk_register_fixed_factor() - Register fixed factor with the
332 	flag = zynqmp_clk_map_common_ccf_flags(nodes->flag);  in zynqmp_clk_register_fixed_factor()
343  * zynqmp_pm_clock_get_parents() - Get the first 3 parents of clock for given id
377  * zynqmp_pm_clock_get_attributes() - Get the attributes of clock for given id
402  * __zynqmp_clock_get_topology() - Get topology data of clock from firmware
417 	for (i = 0; i < ARRAY_SIZE(response->topology); i++) {  in __zynqmp_clock_get_topology()
418 		type = FIELD_GET(CLK_TOPOLOGY_TYPE, response->topology[i]);  in __zynqmp_clock_get_topology()
423 						   response->topology[i]);  in __zynqmp_clock_get_topology()
426 					  response->topology[i]);  in __zynqmp_clock_get_topology()
429 				  response->topology[i]);  in __zynqmp_clock_get_topology()
437  * zynqmp_clock_get_topology() - Get topology of clock from firmware using
468  * __zynqmp_clock_get_parents() - Get parents info of clock from firmware
483 	for (i = 0; i < ARRAY_SIZE(response->parents); i++) {  in __zynqmp_clock_get_parents()
484 		if (response->parents[i] == NA_PARENT)  in __zynqmp_clock_get_parents()
488 		parent->id = FIELD_GET(CLK_PARENTS_ID, response->parents[i]);  in __zynqmp_clock_get_parents()
489 		if (response->parents[i] == DUMMY_PARENT) {  in __zynqmp_clock_get_parents()
490 			strcpy(parent->name, "dummy_name");  in __zynqmp_clock_get_parents()
491 			parent->flag = 0;  in __zynqmp_clock_get_parents()
493 			parent->flag = FIELD_GET(CLK_PARENTS_FLAGS,  in __zynqmp_clock_get_parents()
494 						 response->parents[i]);  in __zynqmp_clock_get_parents()
495 			if (zynqmp_get_clock_name(parent->id, parent->name))  in __zynqmp_clock_get_parents()
505  * zynqmp_clock_get_parents() - Get parents info from firmware using PM_API
537  * zynqmp_get_parent_list() - Create list of parents name
560 			ret = of_property_match_string(np, "clock-names",  in zynqmp_get_parent_list()
567 			       clk_type_postfix[clk_nodes[parents[i].flag - 1].  in zynqmp_get_parent_list()
578  * zynqmp_register_clk_topology() - Register clock topology
605 		if (j != (num_nodes - 1)) {  in zynqmp_register_clk_topology()
634  * zynqmp_register_clocks() - Register clocks
667 		zynqmp_data->hws[i] =  in zynqmp_register_clocks()
674 		if (IS_ERR(zynqmp_data->hws[i])) {  in zynqmp_register_clocks()
676 			       clock[i].clk_name, PTR_ERR(zynqmp_data->hws[i]));  in zynqmp_register_clocks()
684  * zynqmp_get_clock_info() - Get clock information from firmware using PM_API
723 		name.name[sizeof(name.name) - 1] = '\0';  in zynqmp_get_clock_info()
749  * zynqmp_clk_setup() - Setup the clock framework and register clocks
765 		return -ENOMEM;  in zynqmp_clk_setup()
770 		return -ENOMEM;  in zynqmp_clk_setup()
776 	zynqmp_data->num = clock_max_idx;  in zynqmp_clk_setup()
783 	struct device *dev = &pdev->dev;  in zynqmp_clock_probe()
785 	ret = zynqmp_clk_setup(dev->of_node);  in zynqmp_clock_probe()
791 	{.compatible = "xlnx,zynqmp-clk"},
792 	{.compatible = "xlnx,versal-clk"},