clk/zynqmp/clk-gate-zynqmp.c

1 // SPDX-License-Identifier: GPL-2.0
3  * Zynq UltraScale+ MPSoC clock controller
5  *  Copyright (C) 2016-2018 Xilinx
7  * Gated clock implementation
10 #include <linux/clk-provider.h>
12 #include "clk-zynqmp.h"
15  * struct zynqmp_clk_gate - gating clock
16  * @hw:		handle between common and hardware-specific interfaces
17  * @flags:	hardware-specific flags
18  * @clk_id:	Id of clock
29  * zynqmp_clk_gate_enable() - Enable clock
30  * @hw:		handle between common and hardware-specific interfaces
38 	u32 clk_id = gate->clk_id;  in zynqmp_clk_gate_enable()
44 		pr_debug("%s() clock enable failed for %s (id %d), ret = %d\n",  in zynqmp_clk_gate_enable()
51  * zynqmp_clk_gate_disable() - Disable clock
52  * @hw:		handle between common and hardware-specific interfaces
58 	u32 clk_id = gate->clk_id;  in zynqmp_clk_gate_disable()
64 		pr_debug("%s() clock disable failed for %s (id %d), ret = %d\n",  in zynqmp_clk_gate_disable()
69  * zynqmp_clk_gate_is_enabled() - Check clock state
70  * @hw:		handle between common and hardware-specific interfaces
78 	u32 clk_id = gate->clk_id;  in zynqmp_clk_gate_is_enabled()
83 		pr_debug("%s() clock get state failed for %s, ret = %d\n",  in zynqmp_clk_gate_is_enabled()
85 		return -EIO;  in zynqmp_clk_gate_is_enabled()
98  * zynqmp_clk_register_gate() - Register a gate clock with the clock framework
99  * @name:		Name of this clock
100  * @clk_id:		Id of this clock
101  * @parents:		Name of this clock's parents
103  * @nodes:		Clock topology node
105  * Return: clock hardware of the registered clock gate
107 struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,  in zynqmp_clk_register_gate()  argument
120 		return ERR_PTR(-ENOMEM);  in zynqmp_clk_register_gate()
122 	init.name = name;  in zynqmp_clk_register_gate()
125 	init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);  in zynqmp_clk_register_gate()
131 	gate->flags = nodes->type_flag;  in zynqmp_clk_register_gate()
132 	gate->hw.init = &init;  in zynqmp_clk_register_gate()
133 	gate->clk_id = clk_id;  in zynqmp_clk_register_gate()
135 	hw = &gate->hw;  in zynqmp_clk_register_gate()