235 	u32 value, regh, edged, p5en, p5fedge, regval, regval1;  in clk_wzrd_ver_dynamic_reconfig()  local
244 	regval1 = readl(div_addr);  in clk_wzrd_ver_dynamic_reconfig()
245 	regval1 |= WZRD_CLKFBOUT_PREDIV2;  in clk_wzrd_ver_dynamic_reconfig()
246 	regval1 = regval1 & ~(WZRD_CLKFBOUT_EDGE | WZRD_P5EN | WZRD_P5FEDGE);  in clk_wzrd_ver_dynamic_reconfig()
249 		regval1 |= (edged << WZRD_EDGE_SHIFT);  in clk_wzrd_ver_dynamic_reconfig()
253 	regval1 = regval1 | p5en << WZRD_P5EN_SHIFT | p5fedge << WZRD_P5FEDGE_SHIFT;  in clk_wzrd_ver_dynamic_reconfig()
254 	writel(regval1, div_addr);  in clk_wzrd_ver_dynamic_reconfig()
433 	u32 regh, edged, p5en, p5fedge, value2, m, regval, regval1, value;  in clk_wzrd_dynamic_ver_all_nolock()  local
447 	regval1 = readl(divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
449 	regval1 |= WZRD_MULT_PREDIV2;  in clk_wzrd_dynamic_ver_all_nolock()
451 		regval1 = regval1 | WZRD_CLKFBOUT_EDGE;  in clk_wzrd_dynamic_ver_all_nolock()
453 		regval1 = regval1 & ~WZRD_CLKFBOUT_EDGE;  in clk_wzrd_dynamic_ver_all_nolock()
455 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
457 	regval1 = regh | regh << WZRD_CLKFBOUT_H_SHIFT;  in clk_wzrd_dynamic_ver_all_nolock()
458 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
464 	regval1 = FIELD_PREP(WZRD_DIVCLK_EDGE, edged);  in clk_wzrd_dynamic_ver_all_nolock()
465 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
467 	regval1 = regh | regh << WZRD_CLKFBOUT_H_SHIFT;  in clk_wzrd_dynamic_ver_all_nolock()
468 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1, WZRD_DIVCLK));  in clk_wzrd_dynamic_ver_all_nolock()
472 	regval1 = readl(divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
474 	regval1 |= WZRD_CLKFBOUT_PREDIV2;  in clk_wzrd_dynamic_ver_all_nolock()
475 	regval1 = regval1 & ~(WZRD_CLKFBOUT_EDGE | WZRD_P5EN | WZRD_P5FEDGE);  in clk_wzrd_dynamic_ver_all_nolock()
479 		regval1 |= edged << WZRD_CLKFBOUT_H_SHIFT;  in clk_wzrd_dynamic_ver_all_nolock()
485 	regval1 = regval1 | FIELD_PREP(WZRD_P5EN, p5en) | FIELD_PREP(WZRD_P5FEDGE, p5fedge);  in clk_wzrd_dynamic_ver_all_nolock()
486 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()