clk/x86/clk-lgm.c

1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (C) 2020-2022 MaxLinear, Inc.
8 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/intel,lgm-clk.h>
13 #include "clk-cgu.h"
31 #define G_LEDC0_SHIFT		1
62 #define G_PCIE10_SHIFT		1
117 #define CLK_NR_CLKS		(LGM_GCLK_USB2 + 1)
121  * It's more efficient to provide an explicit table due to non-linear
125 	{ .val = 0, .div = 1 },
126 	{ .val = 1, .div = 2 },
146 	{ .val = 1, .div = 12 },
196 		0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
198 		4, PLL_DIV_WIDTH, 25, 1, 0, 0, pll_div),
200 		8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
202 		12, PLL_DIV_WIDTH, 27, 1, 0, 0, pll_div),
204 		PLL_DIV(CGU_PLL2_CFG0), 0, PLL_DIV_WIDTH, 24, 1, 0, 0,
207 		0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
211 		1, 0, 0, pll_div),
214 		8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
218 		0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
221 		0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
231 		0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
234 		4, PLL_DIV_WIDTH, 25, 1, 0, 0, pll_div),
236 		8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
238 		12, PLL_DIV_WIDTH, 27, 1, 0, 0, pll_div),
240 		0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
242 		8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
244 		12, PLL_DIV_WIDTH, 27, 1, 0, 0, pll_div),
247 			 0, 0, 0, 0, 1, 4),
249 			 0, 0, 0, 0, 1, 4),
251 		0, 1, CLK_MUX_ROUND_CLOSEST, 0),
252 	LGM_MUX(LGM_CLK_SDXC, "sdxc", sdxc_p, 0, CGU_IF_CLK1,
253 		1, 1, CLK_MUX_ROUND_CLOSEST, 0),
261 		0, 1, CLK_MUX_ROUND_CLOSEST, 0),
264 			 0, 0, 0, 0, 2, 1),
266 			 CLK_SET_RATE_PARENT, 0, 0, 0, 0, 0, 1, 2),
286 	LGM_GATE(LGM_GCLK_SDXC, "g_sdxc", "sdxc", 0, CGU_GATE0,
409 		 3, PLL_DDIV_WIDTH, 24, 1, 29, 0),
412 		 9, PLL_DDIV_WIDTH, 25, 1, 28, 0),
415 		 15, PLL_DDIV_WIDTH, 26, 1, 28, 0),
418 		 21, PLL_DDIV_WIDTH, 27, 1, 28, 0),
421 		 3, PLL_DDIV_WIDTH, 24, 1, 29, 0),
427 	struct device *dev = &pdev->dev;  in lgm_cgu_probe()
428 	struct device_node *np = dev->of_node;  in lgm_cgu_probe()
434 		return -ENOMEM;  in lgm_cgu_probe()
436 	ctx->clk_data.num = CLK_NR_CLKS;  in lgm_cgu_probe()
438 	ctx->membase = syscon_node_to_regmap(np);  in lgm_cgu_probe()
439 	if (IS_ERR(ctx->membase)) {  in lgm_cgu_probe()
441 		return PTR_ERR(ctx->membase);  in lgm_cgu_probe()
445 	ctx->np = np;  in lgm_cgu_probe()
446 	ctx->dev = dev;  in lgm_cgu_probe()
464 					   &ctx->clk_data);  in lgm_cgu_probe()
468 	{ .compatible = "intel,cgu-lgm" },
475 		   .name = "cgu-lgm",