1 // SPDX-License-Identifier: GPL-2.0-only
3  * Sysctrl clock implementation for ux500 platform.
5  * Copyright (C) 2013 ST-Ericsson SA
9 #include <linux/clk-provider.h>
10 #include <linux/mfd/abx500/ab8500-sysctrl.h>
33 /* Sysctrl clock operations. */
40 	ret = ab8500_sysctrl_write(clk->reg_sel[0], clk->reg_mask[0],  in clk_sysctrl_prepare()
41 				clk->reg_bits[0]);  in clk_sysctrl_prepare()
43 	if (!ret && clk->enable_delay_us)  in clk_sysctrl_prepare()
44 		usleep_range(clk->enable_delay_us, clk->enable_delay_us +  in clk_sysctrl_prepare()
45 			     (clk->enable_delay_us >> 2));  in clk_sysctrl_prepare()
53 	if (ab8500_sysctrl_clear(clk->reg_sel[0], clk->reg_mask[0]))  in clk_sysctrl_unprepare()
54 		dev_err(clk->dev, "clk_sysctrl: %s fail to clear %s.\n",  in clk_sysctrl_unprepare()
62 	return clk->rate;  in clk_sysctrl_recalc_rate()
68 	u8 old_index = clk->parent_index;  in clk_sysctrl_set_parent()
71 	if (clk->reg_sel[old_index]) {  in clk_sysctrl_set_parent()
72 		ret = ab8500_sysctrl_clear(clk->reg_sel[old_index],  in clk_sysctrl_set_parent()
73 					clk->reg_mask[old_index]);  in clk_sysctrl_set_parent()
78 	if (clk->reg_sel[index]) {  in clk_sysctrl_set_parent()
79 		ret = ab8500_sysctrl_write(clk->reg_sel[index],  in clk_sysctrl_set_parent()
80 					clk->reg_mask[index],  in clk_sysctrl_set_parent()
81 					clk->reg_bits[index]);  in clk_sysctrl_set_parent()
83 			if (clk->reg_sel[old_index])  in clk_sysctrl_set_parent()
84 				ab8500_sysctrl_write(clk->reg_sel[old_index],  in clk_sysctrl_set_parent()
85 						clk->reg_mask[old_index],  in clk_sysctrl_set_parent()
86 						clk->reg_bits[old_index]);  in clk_sysctrl_set_parent()
90 	clk->parent_index = index;  in clk_sysctrl_set_parent()
98 	return clk->parent_index;  in clk_sysctrl_get_parent()
136 		return ERR_PTR(-EINVAL);  in clk_reg_sysctrl()
140 		return ERR_PTR(-EINVAL);  in clk_reg_sysctrl()
145 		return ERR_PTR(-ENOMEM);  in clk_reg_sysctrl()
148 	clk->reg_sel[0] = reg_sel[0];  in clk_reg_sysctrl()
149 	clk->reg_bits[0] = reg_bits[0];  in clk_reg_sysctrl()
150 	clk->reg_mask[0] = reg_mask[0];  in clk_reg_sysctrl()
154 		clk->reg_sel[i] = reg_sel[i];  in clk_reg_sysctrl()
155 		clk->reg_bits[i] = reg_bits[i];  in clk_reg_sysctrl()
156 		clk->reg_mask[i] = reg_mask[i];  in clk_reg_sysctrl()
159 	clk->parent_index = 0;  in clk_reg_sysctrl()
160 	clk->rate = rate;  in clk_reg_sysctrl()
161 	clk->enable_delay_us = enable_delay_us;  in clk_reg_sysctrl()
162 	clk->dev = dev;  in clk_reg_sysctrl()
169 	clk->hw.init = &clk_sysctrl_init;  in clk_reg_sysctrl()
171 	clk_reg = devm_clk_register(clk->dev, &clk->hw);  in clk_reg_sysctrl()