Lines Matching full:spll

12 	UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8),		\
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
25 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6)
28 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
32 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
36 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40), \
61 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 8), \
65 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 12), \
69 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 10), \
73 UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20), \
77 UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10), \
87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
92 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
93 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32),
103 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
109 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),
110 UNIPHIER_CLK_FACTOR("spi", 1, "spll", 1, 32),
132 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
135 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),
136 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
137 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32),
147 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */
151 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
152 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48),
166 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1), /* 2400 MHz */
167 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27),
168 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
169 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48),
192 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
194 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
195 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
196 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
211 UNIPHIER_CLK_DIV3("spll", 3, 4, 8),
212 /* Note: both gear1 and gear4 are spll/4. This is not a bug. */
214 "cpll/2", "spll/4", "cpll/3", "spll/3",
215 "spll/4", "spll/8", "cpll/4", "cpll/8"),
217 "mpll/2", "spll/4", "mpll/3", "spll/3",
218 "spll/4", "spll/8", "mpll/4", "mpll/8"),
226 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
229 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
230 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
231 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
256 UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
259 "cpll/2", "spll/2", "cpll/3", "spll/3",
260 "spll/4", "spll/8", "cpll/4", "cpll/8"),
262 "cpll/2", "spll/2", "cpll/3", "spll/3",
263 "spll/4", "spll/8", "cpll/4", "cpll/8"),
265 "s2pll/2", "spll/2", "s2pll/3", "spll/3",
266 "spll/4", "spll/8", "s2pll/4", "s2pll/8"),
272 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
274 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
275 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
276 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
299 UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
302 "cpll/2", "spll/2", "cpll/3", "spll/3",
303 "spll/4", "spll/8", "cpll/4", "cpll/8"),
305 "s2pll/2", "spll/2", "s2pll/3", "spll/3",
306 "spll/4", "spll/8", "s2pll/4", "s2pll/8"),
312 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 32, 1), /* 800 MHz */
313 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 6),
314 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),