Lines Matching +full:40 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include "clk-uniphier.h"
12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
13 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
25 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6)
28 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
29 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
32 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
33 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
36 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40), \
37 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x210c, 0)
40 UNIPHIER_CLK_FACTOR("nand-4x", (idx), "nand", 4, 1)
61 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 8), \
62 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
65 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 12), \
66 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
69 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 10), \
70 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2108, 0)
73 UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20), \
74 UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1)
77 UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10), \
78 UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2)
87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
93 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32),
97 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
103 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
104 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
105 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
106 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
107 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
114 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
116 UNIPHIER_CLK_GATE("ether-gb", 7, "gpll", 0x2104, 5),
118 UNIPHIER_CLK_GATE("ether-phy", 10, "ref", 0x2260, 0),
122 UNIPHIER_CLK_FACTOR("usb30-hsphy0", 16, "upll", 1, 12),
123 UNIPHIER_CLK_FACTOR("usb30-ssphy0", 17, "ref", 1, 1),
124 UNIPHIER_CLK_FACTOR("usb31-ssphy0", 20, "ref", 1, 1),
127 UNIPHIER_PRO4_SYS_CLK_AIO(40),
132 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
133 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
134 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
137 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32),
141 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
147 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */
148 UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */
149 UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125), /* 2949.12 MHz */
150 UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
152 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48),
161 UNIPHIER_PRO5_SYS_CLK_AIO(40),
166 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1), /* 2400 MHz */
169 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48),
175 /* GIO is always clock-enabled: no function for 0x2104 bit6 */
178 /* The document mentions 0x2104 bit 18, but not functional */
179 UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x2104, 19),
180 UNIPHIER_CLK_FACTOR("usb30-ssphy0", 17, "ref", 1, 1),
181 UNIPHIER_CLK_FACTOR("usb30-ssphy1", 18, "ref", 1, 1),
182 UNIPHIER_CLK_GATE("usb31-hsphy0", 20, NULL, 0x2104, 20),
183 UNIPHIER_CLK_FACTOR("usb31-ssphy0", 21, "ref", 1, 1),
185 UNIPHIER_PRO5_SYS_CLK_AIO(40),
190 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 392, 5), /* 1960 MHz */
191 UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* 1600 MHz */
192 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
193 UNIPHIER_CLK_FACTOR("vspll", -1, "ref", 80, 1), /* 2000 MHz */
195 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
196 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
204 UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
205 UNIPHIER_LD11_SYS_CLK_AIO(40),
213 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
216 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
223 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 88, 1), /* ARM: 2200 MHz */
224 UNIPHIER_CLK_FACTOR("gppll", -1, "ref", 52, 1), /* Mali: 1300 MHz */
225 UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* Codec: 1600 MHz */
226 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
227 UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2200 MHz */
228 UNIPHIER_CLK_FACTOR("vppll", -1, "ref", 504, 5), /* 2520 MHz */
230 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
231 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
240 /* GIO is always clock-enabled: no function for 0x210c bit5 */
242 * clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15.
243 * We do not use bit 15 here.
246 UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 12),
247 UNIPHIER_CLK_GATE("usb30-hsphy1", 17, NULL, 0x210c, 13),
248 UNIPHIER_CLK_FACTOR("usb30-ssphy0", 18, "ref", 1, 1),
249 UNIPHIER_CLK_FACTOR("usb30-ssphy1", 19, "ref", 1, 1),
251 UNIPHIER_LD11_SYS_CLK_AIO(40),
258 UNIPHIER_CLK_CPUGEAR("cpu-ca72", 32, 0x8000, 0xf, 8,
261 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
264 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
271 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 104, 1), /* ARM: 2600 MHz */
272 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
273 UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2400 MHz */
275 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
276 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
284 UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x210c, 5), /* =GIO1 */
285 UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x210c, 6), /* =GIO1-1 */
286 UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 16),
287 UNIPHIER_CLK_GATE("usb30-ssphy0", 17, NULL, 0x210c, 18),
288 UNIPHIER_CLK_GATE("usb30-ssphy1", 18, NULL, 0x210c, 20),
289 UNIPHIER_CLK_GATE("usb31-hsphy0", 20, NULL, 0x210c, 17),
290 UNIPHIER_CLK_GATE("usb31-ssphy0", 21, NULL, 0x210c, 19),
294 UNIPHIER_CLK_GATE("sata-phy", 30, NULL, 0x210c, 21),
295 UNIPHIER_LD11_SYS_CLK_AIO(40),
301 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
304 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
311 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 100, 1), /* ARM: 2500 MHz */
312 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 32, 1), /* 800 MHz */
318 UNIPHIER_CLK_GATE("usb30-0", 12, NULL, 0x210c, 16), /* =GIO */
319 UNIPHIER_CLK_GATE("usb30-1", 13, NULL, 0x210c, 20), /* =GIO1P */
320 UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 24),
321 UNIPHIER_CLK_GATE("usb30-ssphy0", 17, NULL, 0x210c, 25),
322 UNIPHIER_CLK_GATE("usb30-ssphy1", 18, NULL, 0x210c, 26),
328 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 5,
337 .name = "sata-ref",