34 /* Static rate multiplier for OMAP4 REGM4XEN clocks */
104  * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
105  * @hw: pointer to the clock to compute the rate for
106  * @parent_rate: clock rate of the DPLL parent
108  * Compute the output rate for the OMAP4 DPLL represented by @clk.
110  * OMAP4 ABE DPLL.  Returns the DPLL's output rate (before M-dividers)
118 	unsigned long rate;  in omap4_dpll_regm4xen_recalc()  local
126 	rate = omap2_get_dpll_rate(clk);  in omap4_dpll_regm4xen_recalc()
131 		rate *= OMAP4430_REGM4XEN_MULT;  in omap4_dpll_regm4xen_recalc()
133 	return rate;  in omap4_dpll_regm4xen_recalc()
137  * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
138  * @hw: struct hw_clk containing the struct clk * of the DPLL to round a rate for
139  * @target_rate: the desired rate of the DPLL
140  * @parent_rate: clock rate of the DPLL parent
142  * Compute the rate that would be programmed into the DPLL hardware
143  * for @clk if set_rate() were to be provided with the rate
145  * needed for the OMAP4 ABE DPLL.  Returns the rounded rate (before
166 	 * target rate without using the 4X multiplier.  in omap4_dpll_regm4xen_round_rate()
175 	 * 4X multiplier is equivalent to dividing the target rate by 4.  in omap4_dpll_regm4xen_round_rate()
192  * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL
193  * @hw: pointer to the clock to determine rate for
194  * @req: target rate request
196  * Determines which DPLL mode to use for reaching a desired rate.
198  * locked, calculates the M,N values for the DPLL via round-rate.
207 	if (!req->rate)  in omap4_dpll_regm4xen_determine_rate()
214 	if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&  in omap4_dpll_regm4xen_determine_rate()
218 		req->rate = omap4_dpll_regm4xen_round_rate(hw, req->rate,  in omap4_dpll_regm4xen_determine_rate()
223 	req->best_parent_rate = req->rate;  in omap4_dpll_regm4xen_determine_rate()