1 // SPDX-License-Identifier: GPL-2.0-only
3  * OMAP4-specific DPLL control functions
20  * can supported when using the DPLL low-power mode. Frequencies are
22  * Status, and Low-Power Operation Mode".
45 	mask = clk->flags & CLOCK_CLKOUTX2 ?  in omap4_dpllmx_allow_gatectrl()
49 	v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg);  in omap4_dpllmx_allow_gatectrl()
52 	ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg);  in omap4_dpllmx_allow_gatectrl()
63 	mask = clk->flags & CLOCK_CLKOUTX2 ?  in omap4_dpllmx_deny_gatectrl()
67 	v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg);  in omap4_dpllmx_deny_gatectrl()
70 	ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg);  in omap4_dpllmx_deny_gatectrl()
79  * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
82  * Calculates if low-power mode can be enabled based upon the last
83  * multiplier and divider values calculated. If low-power mode can be
84  * enabled, then the bit to enable low-power mode is stored in the
86  * criteria for enabling low-power mode as described in the OMAP4430/60
87  * Public TRM section 3.6.3.3.2 "Enable Control, Status, and Low-Power
94 	fint = clk_hw_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1);  in omap4_dpll_lpmode_recalc()
95 	fout = fint * dd->last_rounded_m;  in omap4_dpll_lpmode_recalc()
98 		dd->last_rounded_lpmode = 1;  in omap4_dpll_lpmode_recalc()
100 		dd->last_rounded_lpmode = 0;  in omap4_dpll_lpmode_recalc()
104  * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
110  * OMAP4 ABE DPLL.  Returns the DPLL's output rate (before M-dividers)
121 	if (!clk || !clk->dpll_data)  in omap4_dpll_regm4xen_recalc()
124 	dd = clk->dpll_data;  in omap4_dpll_regm4xen_recalc()
129 	v = ti_clk_ll_ops->clk_readl(&dd->control_reg);  in omap4_dpll_regm4xen_recalc()
137  * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
146  * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
157 	if (!clk || !clk->dpll_data)  in omap4_dpll_regm4xen_round_rate()
158 		return -EINVAL;  in omap4_dpll_regm4xen_round_rate()
160 	dd = clk->dpll_data;  in omap4_dpll_regm4xen_round_rate()
162 	dd->last_rounded_m4xen = 0;  in omap4_dpll_regm4xen_round_rate()
182 	dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;  in omap4_dpll_regm4xen_round_rate()
183 	dd->last_rounded_m4xen = 1;  in omap4_dpll_regm4xen_round_rate()
188 	return dd->last_rounded_rate;  in omap4_dpll_regm4xen_round_rate()
192  * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL
198  * locked, calculates the M,N values for the DPLL via round-rate.
207 	if (!req->rate)  in omap4_dpll_regm4xen_determine_rate()
208 		return -EINVAL;  in omap4_dpll_regm4xen_determine_rate()
210 	dd = clk->dpll_data;  in omap4_dpll_regm4xen_determine_rate()
212 		return -EINVAL;  in omap4_dpll_regm4xen_determine_rate()
214 	if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&  in omap4_dpll_regm4xen_determine_rate()
215 	    (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {  in omap4_dpll_regm4xen_determine_rate()
216 		req->best_parent_hw = dd->clk_bypass;  in omap4_dpll_regm4xen_determine_rate()
218 		req->rate = omap4_dpll_regm4xen_round_rate(hw, req->rate,  in omap4_dpll_regm4xen_determine_rate()
219 						&req->best_parent_rate);  in omap4_dpll_regm4xen_determine_rate()
220 		req->best_parent_hw = dd->clk_ref;  in omap4_dpll_regm4xen_determine_rate()
223 	req->best_parent_rate = req->rate;  in omap4_dpll_regm4xen_determine_rate()