clk/ti/dpll44xx.c

3  * OMAP4-specific DPLL control functions
19  * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
20  * can supported when using the DPLL low-power mode. Frequencies are
79  * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
80  * @dd: pointer to the dpll data structure
104  * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
106  * @parent_rate: clock rate of the DPLL parent
108  * Compute the output rate for the OMAP4 DPLL represented by @clk.
110  * OMAP4 ABE DPLL.  Returns the DPLL's output rate (before M-dividers)
128 	/* regm4xen adds a multiplier of 4 to DPLL calculations */  in omap4_dpll_regm4xen_recalc()
137  * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
138  * @hw: struct hw_clk containing the struct clk * of the DPLL to round a rate for
139  * @target_rate: the desired rate of the DPLL
140  * @parent_rate: clock rate of the DPLL parent
142  * Compute the rate that would be programmed into the DPLL hardware
145  * needed for the OMAP4 ABE DPLL.  Returns the rounded rate (before
146  * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
165 	 * First try to compute the DPLL configuration for  in omap4_dpll_regm4xen_round_rate()
173 	 * If we did not find a valid DPLL configuration, try again, but  in omap4_dpll_regm4xen_round_rate()
192  * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL
196  * Determines which DPLL mode to use for reaching a desired rate.
197  * Checks whether the DPLL shall be in bypass or locked mode, and if
198  * locked, calculates the M,N values for the DPLL via round-rate.