clk/ti/clkt_dpll.c

3  * OMAP2/3/4 DPLL clock functions
25 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
33  * Scale factor to mitigate roundoff errors in DPLL rate rounding.
44  * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
45  * From device data manual section 4.3 "DPLL and DLL Specifications".
57  * _dpll_test_fint - test whether an Fint value is valid for the DPLL
58  * @clk: DPLL struct clk to test
61  * Tests whether a particular divider @n will result in a valid DPLL
62  * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
75 	/* DPLL divider must result in a valid jitter correction val */  in _dpll_test_fint()
121  * _dpll_test_mult - test a DPLL multiplier value
122  * @m: pointer to the DPLL m (multiplier) value under test
123  * @n: current DPLL n (divider) value under test
125  * @target_rate: the desired DPLL rate
126  * @parent_rate: the DPLL's parent clock rate
128  * This code tests a DPLL multiplier value, ensuring that the
130  * the multiplier value itself is valid for the DPLL.  Initially, the
175  * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not
176  * @v: bitfield value of the DPLL enable
178  * Checks given DPLL enable bitfield to see whether the DPLL is in bypass
179  * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.
217 	/* Reparent the struct clk in case the dpll is in bypass */  in omap2_init_dpll_parent()
225  * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
226  * @clk: struct clk * of a DPLL
229  * When locked, the DPLL output depends on the M and N values.  When
231  * or sys_clk.  Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
233  * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
234  * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
235  * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
236  * if the clock @clk is not a DPLL.
248 	/* Return bypass rate if DPLL is bypassed */  in omap2_get_dpll_rate()
268 /* DPLL rate rounding code */
271  * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
272  * @hw: struct clk_hw containing the struct clk * for a DPLL
273  * @target_rate: desired DPLL clock rate
274  * @parent_rate: parent's DPLL clock rate
276  * Given a DPLL and a desired target rate, round the target rate to a
277  * possible, programmable rate for this DPLL.  Attempts to select the
278  * minimum possible n.  Stores the computed (m, n) in the DPLL's
307 	pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",  in omap2_dpll_round_rate()
316 		/* Is the (input clk, divider) pair valid for the DPLL? */  in omap2_dpll_round_rate()
323 		/* Compute the scaled DPLL multiplier, based on the divider */  in omap2_dpll_round_rate()