Lines Matching full:l4
533 "l4-per-clkctrl:00c0:26",
573 { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0008:24" },
574 { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0010:24" },
575 { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0018:24" },
576 { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0020:24" },
577 { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0028:24" },
578 { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0030:24" },
591 { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:00c0:24" },
598 { OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0118:8" },
633 { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4-wkup-clkctrl:0020:24" },
720 DT_CLK(NULL, "cm2_dm10_mux", "l4-per-clkctrl:0008:24"),
721 DT_CLK(NULL, "cm2_dm11_mux", "l4-per-clkctrl:0010:24"),
722 DT_CLK(NULL, "cm2_dm2_mux", "l4-per-clkctrl:0018:24"),
723 DT_CLK(NULL, "cm2_dm3_mux", "l4-per-clkctrl:0020:24"),
724 DT_CLK(NULL, "cm2_dm4_mux", "l4-per-clkctrl:0028:24"),
725 DT_CLK(NULL, "cm2_dm9_mux", "l4-per-clkctrl:0030:24"),
727 DT_CLK(NULL, "dmt1_clk_mux", "l4-wkup-clkctrl:0020:24"),
738 DT_CLK(NULL, "gpio1_dbclk", "l4-wkup-clkctrl:0018:8"),
739 DT_CLK(NULL, "gpio2_dbclk", "l4-per-clkctrl:0040:8"),
740 DT_CLK(NULL, "gpio3_dbclk", "l4-per-clkctrl:0048:8"),
741 DT_CLK(NULL, "gpio4_dbclk", "l4-per-clkctrl:0050:8"),
742 DT_CLK(NULL, "gpio5_dbclk", "l4-per-clkctrl:0058:8"),
743 DT_CLK(NULL, "gpio6_dbclk", "l4-per-clkctrl:0060:8"),
755 DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4-per-clkctrl:00c0:26"),
756 DT_CLK("48096000.mcbsp", "prcm_fck", "l4-per-clkctrl:00c0:26"),
760 DT_CLK(NULL, "per_mcbsp4_gfclk", "l4-per-clkctrl:00c0:24"),
768 DT_CLK(NULL, "slimbus2_fclk_0", "l4-per-clkctrl:0118:8"),
769 DT_CLK(NULL, "slimbus2_fclk_1", "l4-per-clkctrl:0118:9"),
770 DT_CLK(NULL, "slimbus2_slimbus_clk", "l4-per-clkctrl:0118:10"),