Lines Matching full:clkctrl
19 "clk-24mhz-clkctrl:0000:0",
151 "l3-aon-clkctrl:0000:19",
152 "l3-aon-clkctrl:0000:30",
157 "l3-aon-clkctrl:0000:20",
167 "l3-aon-clkctrl:0000:22",
192 { AM3_L3_AON_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l3-aon-clkctrl:0000:24" },
207 { AM3_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk-24mhz-clkctrl:0000:0" },
241 DT_CLK(NULL, "timer_32k_ck", "clk-24mhz-clkctrl:0000:0"),
243 DT_CLK(NULL, "clkdiv32k_ick", "clk-24mhz-clkctrl:0000:0"),
244 DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"),
245 DT_CLK(NULL, "dbg_sysclk_ck", "l3-aon-clkctrl:0000:19"),
246 DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0008:18"),
247 DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0074:18"),
248 DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0078:18"),
249 DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:007c:18"),
250 DT_CLK(NULL, "stm_clk_div_ck", "l3-aon-clkctrl:0000:27"),
251 DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l3-aon-clkctrl:0000:22"),
252 DT_CLK(NULL, "trace_clk_div_ck", "l3-aon-clkctrl:0000:24"),
253 DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l3-aon-clkctrl:0000:20"),
262 "l3-clkctrl:00bc:0",