1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/clk-provider.h>
16 #define ADPLL_PLLSS_MMR_LOCK_OFFSET	0x00	/* Managed by MPPULL */
17 #define ADPLL_PLLSS_MMR_LOCK_ENABLED	0x1f125B64
18 #define ADPLL_PLLSS_MMR_UNLOCK_MAGIC	0x1eda4c3d
20 #define ADPLL_PWRCTRL_OFFSET		0x00
21 #define ADPLL_PWRCTRL_PONIN		5
22 #define ADPLL_PWRCTRL_PGOODIN		4
23 #define ADPLL_PWRCTRL_RET		3
24 #define ADPLL_PWRCTRL_ISORET		2
25 #define ADPLL_PWRCTRL_ISOSCAN		1
26 #define ADPLL_PWRCTRL_OFFMODE		0
28 #define ADPLL_CLKCTRL_OFFSET		0x04
29 #define ADPLL_CLKCTRL_CLKDCOLDOEN	29
30 #define ADPLL_CLKCTRL_IDLE		23
31 #define ADPLL_CLKCTRL_CLKOUTEN		20
32 #define ADPLL_CLKINPHIFSEL_ADPLL_S	19	/* REVISIT: which bit? */
33 #define ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ 19
34 #define ADPLL_CLKCTRL_ULOWCLKEN		18
35 #define ADPLL_CLKCTRL_CLKDCOLDOPWDNZ	17
36 #define ADPLL_CLKCTRL_M2PWDNZ		16
37 #define ADPLL_CLKCTRL_M3PWDNZ_ADPLL_S	15
38 #define ADPLL_CLKCTRL_LOWCURRSTDBY_ADPLL_S 13
39 #define ADPLL_CLKCTRL_LPMODE_ADPLL_S	12
40 #define ADPLL_CLKCTRL_REGM4XEN_ADPLL_S	10
41 #define ADPLL_CLKCTRL_SELFREQDCO_ADPLL_LJ 10
42 #define ADPLL_CLKCTRL_TINITZ		0
44 #define ADPLL_TENABLE_OFFSET		0x08
45 #define ADPLL_TENABLEDIV_OFFSET		0x8c
47 #define ADPLL_M2NDIV_OFFSET		0x10
48 #define ADPLL_M2NDIV_M2			16
49 #define ADPLL_M2NDIV_M2_ADPLL_S_WIDTH	5
50 #define ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH	7
52 #define ADPLL_MN2DIV_OFFSET		0x14
53 #define ADPLL_MN2DIV_N2			16
55 #define ADPLL_FRACDIV_OFFSET		0x18
56 #define ADPLL_FRACDIV_REGSD		24
57 #define ADPLL_FRACDIV_FRACTIONALM	0
58 #define ADPLL_FRACDIV_FRACTIONALM_MASK	0x3ffff
60 #define ADPLL_BWCTRL_OFFSET		0x1c
61 #define ADPLL_BWCTRL_BWCONTROL		1
62 #define ADPLL_BWCTRL_BW_INCR_DECRZ	0
64 #define ADPLL_RESERVED_OFFSET		0x20
66 #define ADPLL_STATUS_OFFSET		0x24
67 #define ADPLL_STATUS_PONOUT		31
68 #define ADPLL_STATUS_PGOODOUT		30
69 #define ADPLL_STATUS_LDOPWDN		29
70 #define ADPLL_STATUS_RECAL_BSTATUS3	28
71 #define ADPLL_STATUS_RECAL_OPPIN	27
72 #define ADPLL_STATUS_PHASELOCK		10
73 #define ADPLL_STATUS_FREQLOCK		9
74 #define ADPLL_STATUS_BYPASSACK		8
75 #define ADPLL_STATUS_LOSSREF		6
76 #define ADPLL_STATUS_CLKOUTENACK	5
77 #define ADPLL_STATUS_LOCK2		4
78 #define ADPLL_STATUS_M2CHANGEACK	3
79 #define ADPLL_STATUS_HIGHJITTER		1
80 #define ADPLL_STATUS_BYPASS		0
81 #define ADPLL_STATUS_PREPARED_MASK	(BIT(ADPLL_STATUS_PHASELOCK) | \
84 #define ADPLL_M3DIV_OFFSET		0x28	/* Only on MPUPLL */
85 #define ADPLL_M3DIV_M3			0
86 #define ADPLL_M3DIV_M3_WIDTH		5
87 #define ADPLL_M3DIV_M3_MASK		0x1f
89 #define ADPLL_RAMPCTRL_OFFSET		0x2c	/* Only on MPUPLL */
90 #define ADPLL_RAMPCTRL_CLKRAMPLEVEL	19
91 #define ADPLL_RAMPCTRL_CLKRAMPRATE	16
92 #define ADPLL_RAMPCTRL_RELOCK_RAMP_EN	0
94 #define MAX_ADPLL_INPUTS		3
95 #define MAX_ADPLL_OUTPUTS		4
96 #define ADPLL_MAX_RETRIES		5
98 #define to_dco(_hw)	container_of(_hw, struct ti_adpll_dco_data, hw)
99 #define to_adpll(_hw)	container_of(_hw, struct ti_adpll_data, dco)
100 #define to_clkout(_hw)	container_of(_hw, struct ti_adpll_clkout_data, hw)
116 #define TI_ADPLL_NR_CLOCKS	(TI_ADPLL_M3 + 1)
162 	const struct ti_adpll_platform_data *c;  member
179 	const char *name;  in ti_adpll_clk_get_name()  local
183 		err = of_property_read_string_index(d->np,  in ti_adpll_clk_get_name()
184 						    "clock-output-names",  in ti_adpll_clk_get_name()
186 						    &name);  in ti_adpll_clk_get_name()
190 		name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s",  in ti_adpll_clk_get_name()
191 				      d->pa, postfix);  in ti_adpll_clk_get_name()
194 	return name;  in ti_adpll_clk_get_name()
197 #define ADPLL_MAX_CON_ID	16	/* See MAX_CON_ID */
200 				int index, int output_index, const char *name,  in ti_adpll_setup_clock()  argument
207 	d->clocks[index].clk = clock;  in ti_adpll_setup_clock()
208 	d->clocks[index].unregister = unregister;  in ti_adpll_setup_clock()
211 	postfix = strrchr(name, '.');  in ti_adpll_setup_clock()
214 			dev_warn(d->dev, "clock %s con_id lookup may fail\n",  in ti_adpll_setup_clock()
215 				 name);  in ti_adpll_setup_clock()
216 		snprintf(con_id, 16, "pll%03lx%s", d->pa & 0xfff, postfix + 1);  in ti_adpll_setup_clock()
219 			return -ENOMEM;  in ti_adpll_setup_clock()
220 		d->clocks[index].cl = cl;  in ti_adpll_setup_clock()
222 		dev_warn(d->dev, "no con_id for clock %s\n", name);  in ti_adpll_setup_clock()
228 	d->outputs.clks[output_index] = clock;  in ti_adpll_setup_clock()
229 	d->outputs.clk_num++;  in ti_adpll_setup_clock()
236 				 int output_index, char *name,  in ti_adpll_init_divider()  argument
246 	child_name = ti_adpll_clk_get_name(d, output_index, name);  in ti_adpll_init_divider()
248 		return -EINVAL;  in ti_adpll_init_divider()
251 	clock = clk_register_divider(d->dev, child_name, parent_name, 0,  in ti_adpll_init_divider()
253 				     &d->lock);  in ti_adpll_init_divider()
255 		dev_err(d->dev, "failed to register divider %s: %li\n",  in ti_adpll_init_divider()
256 			name, PTR_ERR(clock));  in ti_adpll_init_divider()
266 			     char *name, struct clk *clk0,  in ti_adpll_init_mux()  argument
275 	child_name = ti_adpll_clk_get_name(d, -ENODEV, name);  in ti_adpll_init_mux()
277 		return -ENOMEM;  in ti_adpll_init_mux()
280 	clock = clk_register_mux(d->dev, child_name, parents, 2, 0,  in ti_adpll_init_mux()
281 				 reg, shift, 1, 0, &d->lock);  in ti_adpll_init_mux()
283 		dev_err(d->dev, "failed to register mux %s: %li\n",  in ti_adpll_init_mux()
284 			name, PTR_ERR(clock));  in ti_adpll_init_mux()
288 	return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,  in ti_adpll_init_mux()
294 			      int output_index, char *name,  in ti_adpll_init_gate()  argument
304 	child_name = ti_adpll_clk_get_name(d, output_index, name);  in ti_adpll_init_gate()
306 		return -EINVAL;  in ti_adpll_init_gate()
309 	clock = clk_register_gate(d->dev, child_name, parent_name, 0,  in ti_adpll_init_gate()
311 				  &d->lock);  in ti_adpll_init_gate()
313 		dev_err(d->dev, "failed to register gate %s: %li\n",  in ti_adpll_init_gate()
314 			name, PTR_ERR(clock));  in ti_adpll_init_gate()
324 				      char *name,  in ti_adpll_init_fixed_factor()  argument
333 	child_name = ti_adpll_clk_get_name(d, -ENODEV, name);  in ti_adpll_init_fixed_factor()
335 		return -ENOMEM;  in ti_adpll_init_fixed_factor()
338 	clock = clk_register_fixed_factor(d->dev, child_name, parent_name,  in ti_adpll_init_fixed_factor()
343 	return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,  in ti_adpll_init_fixed_factor()
352 	spin_lock_irqsave(&d->lock, flags);  in ti_adpll_set_idle_bypass()
353 	v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);  in ti_adpll_set_idle_bypass()
355 	writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);  in ti_adpll_set_idle_bypass()
356 	spin_unlock_irqrestore(&d->lock, flags);  in ti_adpll_set_idle_bypass()
364 	spin_lock_irqsave(&d->lock, flags);  in ti_adpll_clear_idle_bypass()
365 	v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);  in ti_adpll_clear_idle_bypass()
367 	writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);  in ti_adpll_clear_idle_bypass()
368 	spin_unlock_irqrestore(&d->lock, flags);  in ti_adpll_clear_idle_bypass()
375 	v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);  in ti_adpll_clock_is_bypass()
387 	u32 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);  in ti_adpll_is_locked()
400 	} while (retries--);  in ti_adpll_wait_lock()
402 	dev_err(d->dev, "pll failed to lock\n");  in ti_adpll_wait_lock()
403 	return -ETIMEDOUT;  in ti_adpll_wait_lock()
449 	spin_lock_irqsave(&d->lock, flags);  in ti_adpll_recalc_rate()
450 	frac_m = readl_relaxed(d->regs + ADPLL_FRACDIV_OFFSET);  in ti_adpll_recalc_rate()
452 	rate = (u64)readw_relaxed(d->regs + ADPLL_MN2DIV_OFFSET) << 18;  in ti_adpll_recalc_rate()
455 	divider = (readw_relaxed(d->regs + ADPLL_M2NDIV_OFFSET) + 1) << 18;  in ti_adpll_recalc_rate()
456 	spin_unlock_irqrestore(&d->lock, flags);  in ti_adpll_recalc_rate()
460 	if (d->c->is_type_s) {  in ti_adpll_recalc_rate()
461 		v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);  in ti_adpll_recalc_rate()
491 	d->outputs.clks = devm_kcalloc(d->dev,  in ti_adpll_init_dco()
495 	if (!d->outputs.clks)  in ti_adpll_init_dco()
496 		return -ENOMEM;  in ti_adpll_init_dco()
498 	if (d->c->output_index < 0)  in ti_adpll_init_dco()
503 	init.name = ti_adpll_clk_get_name(d, d->c->output_index, postfix);  in ti_adpll_init_dco()
504 	if (!init.name)  in ti_adpll_init_dco()
505 		return -EINVAL;  in ti_adpll_init_dco()
507 	init.parent_names = d->parent_names;  in ti_adpll_init_dco()
508 	init.num_parents = d->c->nr_max_inputs;  in ti_adpll_init_dco()
511 	d->dco.hw.init = &init;  in ti_adpll_init_dco()
513 	if (d->c->is_type_s)  in ti_adpll_init_dco()
519 	err = ti_adpll_init_divider(d, TI_ADPLL_N2, -ENODEV, "n2",  in ti_adpll_init_dco()
520 				    d->parent_clocks[TI_ADPLL_CLKINP],  in ti_adpll_init_dco()
521 				    d->regs + ADPLL_MN2DIV_OFFSET,  in ti_adpll_init_dco()
526 	clock = devm_clk_register(d->dev, &d->dco.hw);  in ti_adpll_init_dco()
530 	return ti_adpll_setup_clock(d, clock, TI_ADPLL_DCO, d->c->output_index,  in ti_adpll_init_dco()
531 				    init.name, NULL);  in ti_adpll_init_dco()
537 	struct clk_hw *gate_hw = &co->gate.hw;  in ti_adpll_clkout_enable()
547 	struct clk_hw *gate_hw = &co->gate.hw;  in ti_adpll_clkout_disable()
556 	struct clk_hw *gate_hw = &co->gate.hw;  in ti_adpll_clkout_is_enabled()
567 	struct ti_adpll_data *d = co->adpll;  in ti_adpll_clkout_get_parent()
575 				char *name, struct clk *clk0,  in ti_adpll_init_clkout()  argument
586 	co = devm_kzalloc(d->dev, sizeof(*co), GFP_KERNEL);  in ti_adpll_init_clkout()
588 		return -ENOMEM;  in ti_adpll_init_clkout()
589 	co->adpll = d;  in ti_adpll_init_clkout()
591 	err = of_property_read_string_index(d->np,  in ti_adpll_init_clkout()
592 					    "clock-output-names",  in ti_adpll_init_clkout()
598 	ops = devm_kzalloc(d->dev, sizeof(*ops), GFP_KERNEL);  in ti_adpll_init_clkout()
600 		return -ENOMEM;  in ti_adpll_init_clkout()
602 	init.name = child_name;  in ti_adpll_init_clkout()
605 	co->hw.init = &init;  in ti_adpll_init_clkout()
611 	ops->get_parent = ti_adpll_clkout_get_parent;  in ti_adpll_init_clkout()
612 	ops->determine_rate = __clk_mux_determine_rate;  in ti_adpll_init_clkout()
614 		co->gate.lock = &d->lock;  in ti_adpll_init_clkout()
615 		co->gate.reg = d->regs + ADPLL_CLKCTRL_OFFSET;  in ti_adpll_init_clkout()
616 		co->gate.bit_idx = gate_bit;  in ti_adpll_init_clkout()
617 		ops->enable = ti_adpll_clkout_enable;  in ti_adpll_init_clkout()
618 		ops->disable = ti_adpll_clkout_disable;  in ti_adpll_init_clkout()
619 		ops->is_enabled = ti_adpll_clkout_is_enabled;  in ti_adpll_init_clkout()
622 	clock = devm_clk_register(d->dev, &co->hw);  in ti_adpll_init_clkout()
624 		dev_err(d->dev, "failed to register output %s: %li\n",  in ti_adpll_init_clkout()
625 			name, PTR_ERR(clock));  in ti_adpll_init_clkout()
637 	if (!d->c->is_type_s)  in ti_adpll_init_children_adpll_s()
642 				d->clocks[TI_ADPLL_N2].clk,  in ti_adpll_init_children_adpll_s()
643 				d->parent_clocks[TI_ADPLL_CLKINPULOW],  in ti_adpll_init_children_adpll_s()
644 				d->regs + ADPLL_CLKCTRL_OFFSET,  in ti_adpll_init_children_adpll_s()
650 	err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV, "m2",  in ti_adpll_init_children_adpll_s()
651 				    d->clocks[TI_ADPLL_DCO].clk,  in ti_adpll_init_children_adpll_s()
652 				    d->regs + ADPLL_M2NDIV_OFFSET,  in ti_adpll_init_children_adpll_s()
661 					 d->clocks[TI_ADPLL_M2].clk,  in ti_adpll_init_children_adpll_s()
669 				   d->clocks[TI_ADPLL_DIV2].clk,  in ti_adpll_init_children_adpll_s()
670 				   d->clocks[TI_ADPLL_BYPASS].clk);  in ti_adpll_init_children_adpll_s()
676 				   "clkout2", d->clocks[TI_ADPLL_M2].clk,  in ti_adpll_init_children_adpll_s()
677 				   d->clocks[TI_ADPLL_BYPASS].clk);  in ti_adpll_init_children_adpll_s()
682 	if (d->parent_clocks[TI_ADPLL_CLKINPHIF]) {  in ti_adpll_init_children_adpll_s()
684 					d->clocks[TI_ADPLL_DCO].clk,  in ti_adpll_init_children_adpll_s()
685 					d->parent_clocks[TI_ADPLL_CLKINPHIF],  in ti_adpll_init_children_adpll_s()
686 					d->regs + ADPLL_CLKCTRL_OFFSET,  in ti_adpll_init_children_adpll_s()
694 				    d->clocks[TI_ADPLL_HIF].clk,  in ti_adpll_init_children_adpll_s()
695 				    d->regs + ADPLL_M3DIV_OFFSET,  in ti_adpll_init_children_adpll_s()
711 	if (d->c->is_type_s)  in ti_adpll_init_children_adpll_lj()
716 				 "clkdcoldo", d->clocks[TI_ADPLL_DCO].clk,  in ti_adpll_init_children_adpll_lj()
717 				 d->regs + ADPLL_CLKCTRL_OFFSET,  in ti_adpll_init_children_adpll_lj()
723 	err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV,  in ti_adpll_init_children_adpll_lj()
724 				    "m2", d->clocks[TI_ADPLL_DCO].clk,  in ti_adpll_init_children_adpll_lj()
725 				    d->regs + ADPLL_M2NDIV_OFFSET,  in ti_adpll_init_children_adpll_lj()
734 				 "clkoutldo", d->clocks[TI_ADPLL_M2].clk,  in ti_adpll_init_children_adpll_lj()
735 				 d->regs + ADPLL_CLKCTRL_OFFSET,  in ti_adpll_init_children_adpll_lj()
743 				d->clocks[TI_ADPLL_N2].clk,  in ti_adpll_init_children_adpll_lj()
744 				d->parent_clocks[TI_ADPLL_CLKINPULOW],  in ti_adpll_init_children_adpll_lj()
745 				d->regs + ADPLL_CLKCTRL_OFFSET,  in ti_adpll_init_children_adpll_lj()
753 				   d->clocks[TI_ADPLL_M2].clk,  in ti_adpll_init_children_adpll_lj()
754 				   d->clocks[TI_ADPLL_BYPASS].clk);  in ti_adpll_init_children_adpll_lj()
765 	for (i = TI_ADPLL_M3; i >= 0; i--) {  in ti_adpll_free_resources()
766 		struct ti_adpll_clock *ac = &d->clocks[i];  in ti_adpll_free_resources()
768 		if (!ac || IS_ERR_OR_NULL(ac->clk))  in ti_adpll_free_resources()
770 		if (ac->cl)  in ti_adpll_free_resources()
771 			clkdev_drop(ac->cl);  in ti_adpll_free_resources()
772 		if (ac->unregister)  in ti_adpll_free_resources()
773 			ac->unregister(ac->clk);  in ti_adpll_free_resources()
791 	if (d->c->is_type_s) {  in ti_adpll_init_registers()
793 		ti_adpll_unlock_all(d->iobase + ADPLL_PLLSS_MMR_LOCK_OFFSET);  in ti_adpll_init_registers()
796 	d->regs = d->iobase + register_offset + ADPLL_PWRCTRL_OFFSET;  in ti_adpll_init_registers()
807 	nr_inputs = of_clk_get_parent_count(d->np);  in ti_adpll_init_inputs()
808 	if (nr_inputs < d->c->nr_max_inputs) {  in ti_adpll_init_inputs()
809 		dev_err(d->dev, error, nr_inputs);  in ti_adpll_init_inputs()
810 		return -EINVAL;  in ti_adpll_init_inputs()
812 	of_clk_parent_fill(d->np, d->parent_names, nr_inputs);  in ti_adpll_init_inputs()
814 	clock = devm_clk_get(d->dev, d->parent_names[0]);  in ti_adpll_init_inputs()
816 		dev_err(d->dev, "could not get clkinp\n");  in ti_adpll_init_inputs()
819 	d->parent_clocks[TI_ADPLL_CLKINP] = clock;  in ti_adpll_init_inputs()
821 	clock = devm_clk_get(d->dev, d->parent_names[1]);  in ti_adpll_init_inputs()
823 		dev_err(d->dev, "could not get clkinpulow clock\n");  in ti_adpll_init_inputs()
826 	d->parent_clocks[TI_ADPLL_CLKINPULOW] = clock;  in ti_adpll_init_inputs()
828 	if (d->c->is_type_s) {  in ti_adpll_init_inputs()
829 		clock =  devm_clk_get(d->dev, d->parent_names[2]);  in ti_adpll_init_inputs()
831 			dev_err(d->dev, "could not get clkinphif clock\n");  in ti_adpll_init_inputs()
834 		d->parent_clocks[TI_ADPLL_CLKINPHIF] = clock;  in ti_adpll_init_inputs()
849 	.nr_max_inputs = MAX_ADPLL_INPUTS - 1,
850 	.nr_max_outputs = MAX_ADPLL_OUTPUTS - 1,
851 	.output_index = -EINVAL,
855 	{ .compatible = "ti,dm814-adpll-s-clock", &ti_adpll_type_s },
856 	{ .compatible = "ti,dm814-adpll-lj-clock", &ti_adpll_type_lj },
863 	struct device_node *node = pdev->dev.of_node;  in ti_adpll_probe()
864 	struct device *dev = &pdev->dev;  in ti_adpll_probe()
871 		return -ENOMEM;  in ti_adpll_probe()
872 	d->dev = dev;  in ti_adpll_probe()
873 	d->np = node;  in ti_adpll_probe()
874 	d->c = device_get_match_data(dev);  in ti_adpll_probe()
875 	dev_set_drvdata(d->dev, d);  in ti_adpll_probe()
876 	spin_lock_init(&d->lock);  in ti_adpll_probe()
878 	d->iobase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in ti_adpll_probe()
879 	if (IS_ERR(d->iobase))  in ti_adpll_probe()
880 		return PTR_ERR(d->iobase);  in ti_adpll_probe()
881 	d->pa = res->start;  in ti_adpll_probe()
891 	d->clocks = devm_kcalloc(d->dev,  in ti_adpll_probe()
895 	if (!d->clocks)  in ti_adpll_probe()
896 		return -ENOMEM;  in ti_adpll_probe()
911 	err = of_clk_add_provider(d->np, of_clk_src_onecell_get, &d->outputs);  in ti_adpll_probe()
926 	struct ti_adpll_data *d = dev_get_drvdata(&pdev->dev);  in ti_adpll_remove()
933 		.name = "ti-adpll",
953 MODULE_ALIAS("platform:dm814-adpll-clock");