clk/thead/clk-th1520-ap.c

1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
10 #include <linux/clk-provider.h>
131 	regmap_read(common->map, common->cfg0, &val);  in ccu_get_parent_helper()
132 	parent = val >> mux->shift;  in ccu_get_parent_helper()
133 	parent &= GENMASK(mux->width - 1, 0);  in ccu_get_parent_helper()
142 	return regmap_update_bits(common->map, common->cfg0,  in ccu_set_parent_helper()
143 			GENMASK(mux->width - 1, 0) << mux->shift,  in ccu_set_parent_helper()
144 			index << mux->shift);  in ccu_set_parent_helper()
151 	regmap_update_bits(common->map, common->cfg0,  in ccu_disable_helper()
163 	ret = regmap_update_bits(common->map, common->cfg0, gate, gate);  in ccu_enable_helper()
164 	regmap_read(common->map, common->cfg0, &val);  in ccu_enable_helper()
175 	regmap_read(common->map, common->cfg0, &val);  in ccu_is_enabled_helper()
186 	regmap_read(cd->common.map, cd->common.cfg0, &val);  in ccu_div_recalc_rate()
187 	val = val >> cd->div.shift;  in ccu_div_recalc_rate()
188 	val &= GENMASK(cd->div.width - 1, 0);  in ccu_div_recalc_rate()
190 				   cd->div.flags, cd->div.width);  in ccu_div_recalc_rate()
199 	return ccu_get_parent_helper(&cd->common, &cd->mux);  in ccu_div_get_parent()
206 	return ccu_set_parent_helper(&cd->common, &cd->mux, index);  in ccu_div_set_parent()
213 	ccu_disable_helper(&cd->common, cd->enable);  in ccu_div_disable()
220 	return ccu_enable_helper(&cd->common, cd->enable);  in ccu_div_enable()
227 	return ccu_is_enabled_helper(&cd->common, cd->enable);  in ccu_div_is_enabled()
248 	regmap_read(pll->common.map, pll->common.cfg0, &cfg0);  in th1520_pll_vco_recalc_rate()
249 	regmap_read(pll->common.map, pll->common.cfg1, &cfg1);  in th1520_pll_vco_recalc_rate()
271 	regmap_read(pll->common.map, pll->common.cfg0, &cfg0);  in th1520_pll_postdiv_recalc_rate()
272 	regmap_read(pll->common.map, pll->common.cfg1, &cfg1);  in th1520_pll_postdiv_recalc_rate()
309 		.hw.init	= CLK_HW_INIT_PARENTS_DATA("cpu-pll0",
321 		.hw.init	= CLK_HW_INIT_PARENTS_DATA("cpu-pll1",
333 		.hw.init	= CLK_HW_INIT_PARENTS_DATA("gmac-pll",
353 		.hw.init	= CLK_HW_INIT_PARENTS_DATA("video-pll",
373 		.hw.init	= CLK_HW_INIT_PARENTS_DATA("dpu0-pll",
389 		.hw.init	= CLK_HW_INIT_PARENTS_DATA("dpu1-pll",
405 		.hw.init	= CLK_HW_INIT_PARENTS_DATA("tee-pll",
422 		.hw.init	= CLK_HW_INIT_PARENTS_DATA("c910-i0",
457 		.hw.init	= CLK_HW_INIT_PARENTS_DATA("ahb2-cpusys-hclk",
477 		.hw.init	= CLK_HW_INIT_PARENTS_HW("apb3-cpusys-pclk",
493 		.hw.init	= CLK_HW_INIT_PARENTS_HW("axi4-cpusys2-aclk",
515 		.hw.init	= CLK_HW_INIT_PARENTS_DATA("axi-aclk",
538 		.hw.init	= CLK_HW_INIT_PARENTS_DATA("perisys-ahb-hclk",
558 		.hw.init	= CLK_HW_INIT_PARENTS_HW("perisys-apb-pclk",
574 		.hw.init	= CLK_HW_INIT_PARENTS_HW("peri2sys-apb-pclk",
657 		.hw.init	= CLK_HW_INIT_PARENTS_DATA("apb-pclk",
700 		.hw.init	= CLK_HW_INIT_PARENTS_HW("vi-ahb",
713 		.hw.init	= CLK_HW_INIT_PARENTS_HW("vo-axi",
725 		.hw.init	= CLK_HW_INIT_PARENTS_HW("vp-apb",
738 		.hw.init	= CLK_HW_INIT_PARENTS_HW("vp-axi",
784 static CCU_GATE(CLK_AON2CPU_A2X, aon2cpu_a2x_clk, "aon2cpu-a2x", axi4_cpusys2_aclk_pd,
786 static CCU_GATE(CLK_X2X_CPUSYS, x2x_cpusys_clk, "x2x-cpusys", axi4_cpusys2_aclk_pd,
788 static CCU_GATE(CLK_CPU2AON_X2H, cpu2aon_x2h_clk, "cpu2aon-x2h", axi_aclk_pd, 0x138, BIT(8), 0);
789 static CCU_GATE(CLK_CPU2PERI_X2H, cpu2peri_x2h_clk, "cpu2peri-x2h", axi4_cpusys2_aclk_pd,
791 static CCU_GATE(CLK_PERISYS_APB1_HCLK, perisys_apb1_hclk, "perisys-apb1-hclk", perisys_ahb_hclk_pd,
793 static CCU_GATE(CLK_PERISYS_APB2_HCLK, perisys_apb2_hclk, "perisys-apb2-hclk", perisys_ahb_hclk_pd,
795 static CCU_GATE(CLK_PERISYS_APB3_HCLK, perisys_apb3_hclk, "perisys-apb3-hclk", perisys_ahb_hclk_pd,
797 static CCU_GATE(CLK_PERISYS_APB4_HCLK, perisys_apb4_hclk, "perisys-apb4-hclk", perisys_ahb_hclk_pd,
799 static CCU_GATE(CLK_NPU_AXI, npu_axi_clk, "npu-axi", axi_aclk_pd, 0x1c8, BIT(5), 0);
801 static CCU_GATE(CLK_EMMC_SDIO, emmc_sdio_clk, "emmc-sdio", video_pll_clk_pd, 0x204, BIT(30), 0);
806 static CCU_GATE(CLK_GMAC_AXI, gmac_axi_clk, "gmac-axi", axi4_cpusys2_aclk_pd, 0x204, BIT(21), 0);
807 static CCU_GATE(CLK_GPIO3, gpio3_clk, "gpio3-clk", peri2sys_apb_pclk_pd, 0x204, BIT(20), 0);
813 static CCU_GATE(CLK_UART0_PCLK, uart0_pclk, "uart0-pclk", perisys_apb_pclk_pd, 0x204, BIT(14), 0);
814 static CCU_GATE(CLK_UART1_PCLK, uart1_pclk, "uart1-pclk", perisys_apb_pclk_pd, 0x204, BIT(13), 0);
815 static CCU_GATE(CLK_UART2_PCLK, uart2_pclk, "uart2-pclk", perisys_apb_pclk_pd, 0x204, BIT(12), 0);
816 static CCU_GATE(CLK_UART3_PCLK, uart3_pclk, "uart3-pclk", perisys_apb_pclk_pd, 0x204, BIT(11), 0);
817 static CCU_GATE(CLK_UART4_PCLK, uart4_pclk, "uart4-pclk", perisys_apb_pclk_pd, 0x204, BIT(10), 0);
818 static CCU_GATE(CLK_UART5_PCLK, uart5_pclk, "uart5-pclk", perisys_apb_pclk_pd, 0x204, BIT(9), 0);
819 static CCU_GATE(CLK_GPIO0, gpio0_clk, "gpio0-clk", perisys_apb_pclk_pd, 0x204, BIT(8), 0);
820 static CCU_GATE(CLK_GPIO1, gpio1_clk, "gpio1-clk", perisys_apb_pclk_pd, 0x204, BIT(7), 0);
821 static CCU_GATE(CLK_GPIO2, gpio2_clk, "gpio2-clk", peri2sys_apb_pclk_pd, 0x204, BIT(6), 0);
843 static CLK_FIXED_FACTOR_HW(gmac_pll_clk_100m, "gmac-pll-clk-100m",
856 		.hw.init	= CLK_HW_INIT_PARENTS_DATA("uart-sclk",
970 	struct device *dev = &pdev->dev;  in th1520_clk_probe()
980 		return -ENOMEM;  in th1520_clk_probe()
982 	priv->num = NR_CLKS;  in th1520_clk_probe()
993 		struct ccu_pll *cp = hw_to_ccu_pll(&th1520_pll_clks[i]->hw);  in th1520_clk_probe()
995 		th1520_pll_clks[i]->map = map;  in th1520_clk_probe()
997 		ret = devm_clk_hw_register(dev, &th1520_pll_clks[i]->hw);  in th1520_clk_probe()
1001 		priv->hws[cp->common.clkid] = &cp->common.hw;  in th1520_clk_probe()
1005 		struct ccu_div *cd = hw_to_ccu_div(&th1520_div_clks[i]->hw);  in th1520_clk_probe()
1007 		th1520_div_clks[i]->map = map;  in th1520_clk_probe()
1009 		ret = devm_clk_hw_register(dev, &th1520_div_clks[i]->hw);  in th1520_clk_probe()
1013 		priv->hws[cd->common.clkid] = &cd->common.hw;  in th1520_clk_probe()
1017 		struct ccu_mux *cm = hw_to_ccu_mux(&th1520_mux_clks[i]->hw);  in th1520_clk_probe()
1018 		const struct clk_init_data *init = cm->common.hw.init;  in th1520_clk_probe()
1020 		th1520_mux_clks[i]->map = map;  in th1520_clk_probe()
1022 								init->name,  in th1520_clk_probe()
1023 								init->parent_data,  in th1520_clk_probe()
1024 								init->num_parents,  in th1520_clk_probe()
1026 								base + cm->common.cfg0,  in th1520_clk_probe()
1027 								cm->mux.shift,  in th1520_clk_probe()
1028 								cm->mux.width,  in th1520_clk_probe()
1033 		priv->hws[cm->common.clkid] = hw;  in th1520_clk_probe()
1037 		struct ccu_gate *cg = hw_to_ccu_gate(&th1520_gate_clks[i]->hw);  in th1520_clk_probe()
1039 		th1520_gate_clks[i]->map = map;  in th1520_clk_probe()
1042 							   cg->common.hw.init->name,  in th1520_clk_probe()
1043 							   cg->common.hw.init->parent_data,  in th1520_clk_probe()
1044 							   0, base + cg->common.cfg0,  in th1520_clk_probe()
1045 							   ffs(cg->enable) - 1, 0, NULL);  in th1520_clk_probe()
1049 		priv->hws[cg->common.clkid] = hw;  in th1520_clk_probe()
1055 	priv->hws[CLK_OSC12M] = &osc12m_clk.hw;  in th1520_clk_probe()
1060 	priv->hws[CLK_PLL_GMAC_100M] = &gmac_pll_clk_100m.hw;  in th1520_clk_probe()
1071 		.compatible = "thead,th1520-clk-ap",
1080 		.name	= "th1520-clk",
1086 MODULE_DESCRIPTION("T-HEAD TH1520 AP Clock driver");