Lines Matching +full:0 +full:x150
19 #define TH1520_PLL_REFDIV GENMASK(5, 0)
22 #define TH1520_PLL_FRAC GENMASK(23, 0)
133 parent &= GENMASK(mux->width - 1, 0); in ccu_get_parent_helper()
143 GENMASK(mux->width - 1, 0) << mux->shift, in ccu_set_parent_helper()
161 return 0; in ccu_enable_helper()
188 val &= GENMASK(cd->div.width - 1, 0); in ccu_div_recalc_rate()
301 { .index = 0 }
307 .cfg0 = 0x000,
308 .cfg1 = 0x004,
312 0),
319 .cfg0 = 0x010,
320 .cfg1 = 0x014,
324 0),
331 .cfg0 = 0x020,
332 .cfg1 = 0x024,
336 0),
351 .cfg0 = 0x030,
352 .cfg1 = 0x034,
356 0),
371 .cfg0 = 0x040,
372 .cfg1 = 0x044,
376 0),
387 .cfg0 = 0x050,
388 .cfg1 = 0x054,
392 0),
403 .cfg0 = 0x060,
404 .cfg1 = 0x064,
408 0),
414 { .index = 0 }
421 .cfg0 = 0x100,
425 0),
435 .mux = TH_CCU_ARG(0, 1),
438 .cfg0 = 0x100,
442 0),
448 { .index = 0 }
452 .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
456 .cfg0 = 0x120,
460 0),
473 .div = TH_CCU_ARG(0, 3),
476 .cfg0 = 0x130,
480 0),
489 .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
492 .cfg0 = 0x134,
496 0),
506 { .index = 0 }
510 .div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED),
514 .cfg0 = 0x138,
518 0),
528 { .index = 0 },
533 .div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED),
537 .cfg0 = 0x140,
541 0),
554 .div = TH_CCU_ARG(0, 3),
557 .cfg0 = 0x150,
561 0),
573 .cfg0 = 0x150,
577 0),
585 static CLK_FIXED_FACTOR_FW_NAME(osc12m_clk, "osc_12m", "osc_24m", 2, 1, 0);
591 .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
595 .cfg0 = 0x1b4,
599 0),
605 .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
609 .cfg0 = 0x1b8,
613 0),
619 .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
623 .cfg0 = 0x1bc,
627 0),
633 .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
637 .cfg0 = 0x1c0,
641 0),
647 { .index = 0 },
652 .div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED),
656 .cfg0 = 0x1c4,
660 0),
671 .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
675 .cfg0 = 0x1c8,
679 0),
687 .cfg0 = 0x1d0,
691 0),
696 .div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED),
699 .cfg0 = 0x1d0,
703 0),
709 .div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED),
712 .cfg0 = 0x1dc,
716 0),
721 .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
724 .cfg0 = 0x1e0,
728 0),
737 .cfg0 = 0x1e0,
747 .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
750 .cfg0 = 0x1e4,
754 0),
759 .div = TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED),
762 .cfg0 = 0x1e8,
766 0),
771 .div = TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED),
774 .cfg0 = 0x1ec,
778 0),
782 static CCU_GATE(CLK_BROM, brom_clk, "brom", ahb2_cpusys_hclk_pd, 0x100, BIT(4), 0);
783 static CCU_GATE(CLK_BMU, bmu_clk, "bmu", axi4_cpusys2_aclk_pd, 0x100, BIT(5), 0);
785 0x134, BIT(8), 0);
787 0x134, BIT(7), 0);
788 static CCU_GATE(CLK_CPU2AON_X2H, cpu2aon_x2h_clk, "cpu2aon-x2h", axi_aclk_pd, 0x138, BIT(8), 0);
790 0x140, BIT(9), 0);
792 0x150, BIT(9), 0);
794 0x150, BIT(10), 0);
796 0x150, BIT(11), 0);
798 0x150, BIT(12), 0);
799 static CCU_GATE(CLK_NPU_AXI, npu_axi_clk, "npu-axi", axi_aclk_pd, 0x1c8, BIT(5), 0);
800 static CCU_GATE(CLK_CPU2VP, cpu2vp_clk, "cpu2vp", axi_aclk_pd, 0x1e0, BIT(13), 0);
801 static CCU_GATE(CLK_EMMC_SDIO, emmc_sdio_clk, "emmc-sdio", video_pll_clk_pd, 0x204, BIT(30), 0);
802 static CCU_GATE(CLK_GMAC1, gmac1_clk, "gmac1", gmac_pll_clk_pd, 0x204, BIT(26), 0);
803 static CCU_GATE(CLK_PADCTRL1, padctrl1_clk, "padctrl1", perisys_apb_pclk_pd, 0x204, BIT(24), 0);
804 static CCU_GATE(CLK_DSMART, dsmart_clk, "dsmart", perisys_apb_pclk_pd, 0x204, BIT(23), 0);
805 static CCU_GATE(CLK_PADCTRL0, padctrl0_clk, "padctrl0", perisys_apb_pclk_pd, 0x204, BIT(22), 0);
806 static CCU_GATE(CLK_GMAC_AXI, gmac_axi_clk, "gmac-axi", axi4_cpusys2_aclk_pd, 0x204, BIT(21), 0);
807 static CCU_GATE(CLK_GPIO3, gpio3_clk, "gpio3-clk", peri2sys_apb_pclk_pd, 0x204, BIT(20), 0);
808 static CCU_GATE(CLK_GMAC0, gmac0_clk, "gmac0", gmac_pll_clk_pd, 0x204, BIT(19), 0);
809 static CCU_GATE(CLK_PWM, pwm_clk, "pwm", perisys_apb_pclk_pd, 0x204, BIT(18), 0);
810 static CCU_GATE(CLK_QSPI0, qspi0_clk, "qspi0", video_pll_clk_pd, 0x204, BIT(17), 0);
811 static CCU_GATE(CLK_QSPI1, qspi1_clk, "qspi1", video_pll_clk_pd, 0x204, BIT(16), 0);
812 static CCU_GATE(CLK_SPI, spi_clk, "spi", video_pll_clk_pd, 0x204, BIT(15), 0);
813 static CCU_GATE(CLK_UART0_PCLK, uart0_pclk, "uart0-pclk", perisys_apb_pclk_pd, 0x204, BIT(14), 0);
814 static CCU_GATE(CLK_UART1_PCLK, uart1_pclk, "uart1-pclk", perisys_apb_pclk_pd, 0x204, BIT(13), 0);
815 static CCU_GATE(CLK_UART2_PCLK, uart2_pclk, "uart2-pclk", perisys_apb_pclk_pd, 0x204, BIT(12), 0);
816 static CCU_GATE(CLK_UART3_PCLK, uart3_pclk, "uart3-pclk", perisys_apb_pclk_pd, 0x204, BIT(11), 0);
817 static CCU_GATE(CLK_UART4_PCLK, uart4_pclk, "uart4-pclk", perisys_apb_pclk_pd, 0x204, BIT(10), 0);
818 static CCU_GATE(CLK_UART5_PCLK, uart5_pclk, "uart5-pclk", perisys_apb_pclk_pd, 0x204, BIT(9), 0);
819 static CCU_GATE(CLK_GPIO0, gpio0_clk, "gpio0-clk", perisys_apb_pclk_pd, 0x204, BIT(8), 0);
820 static CCU_GATE(CLK_GPIO1, gpio1_clk, "gpio1-clk", perisys_apb_pclk_pd, 0x204, BIT(7), 0);
821 static CCU_GATE(CLK_GPIO2, gpio2_clk, "gpio2-clk", peri2sys_apb_pclk_pd, 0x204, BIT(6), 0);
822 static CCU_GATE(CLK_I2C0, i2c0_clk, "i2c0", perisys_apb_pclk_pd, 0x204, BIT(5), 0);
823 static CCU_GATE(CLK_I2C1, i2c1_clk, "i2c1", perisys_apb_pclk_pd, 0x204, BIT(4), 0);
824 static CCU_GATE(CLK_I2C2, i2c2_clk, "i2c2", perisys_apb_pclk_pd, 0x204, BIT(3), 0);
825 static CCU_GATE(CLK_I2C3, i2c3_clk, "i2c3", perisys_apb_pclk_pd, 0x204, BIT(2), 0);
826 static CCU_GATE(CLK_I2C4, i2c4_clk, "i2c4", perisys_apb_pclk_pd, 0x204, BIT(1), 0);
827 static CCU_GATE(CLK_I2C5, i2c5_clk, "i2c5", perisys_apb_pclk_pd, 0x204, BIT(0), 0);
828 static CCU_GATE(CLK_SPINLOCK, spinlock_clk, "spinlock", ahb2_cpusys_hclk_pd, 0x208, BIT(10), 0);
829 static CCU_GATE(CLK_DMA, dma_clk, "dma", axi4_cpusys2_aclk_pd, 0x208, BIT(8), 0);
830 static CCU_GATE(CLK_MBOX0, mbox0_clk, "mbox0", apb3_cpusys_pclk_pd, 0x208, BIT(7), 0);
831 static CCU_GATE(CLK_MBOX1, mbox1_clk, "mbox1", apb3_cpusys_pclk_pd, 0x208, BIT(6), 0);
832 static CCU_GATE(CLK_MBOX2, mbox2_clk, "mbox2", apb3_cpusys_pclk_pd, 0x208, BIT(5), 0);
833 static CCU_GATE(CLK_MBOX3, mbox3_clk, "mbox3", apb3_cpusys_pclk_pd, 0x208, BIT(4), 0);
834 static CCU_GATE(CLK_WDT0, wdt0_clk, "wdt0", apb3_cpusys_pclk_pd, 0x208, BIT(3), 0);
835 static CCU_GATE(CLK_WDT1, wdt1_clk, "wdt1", apb3_cpusys_pclk_pd, 0x208, BIT(2), 0);
836 static CCU_GATE(CLK_TIMER0, timer0_clk, "timer0", apb3_cpusys_pclk_pd, 0x208, BIT(1), 0);
837 static CCU_GATE(CLK_TIMER1, timer1_clk, "timer1", apb3_cpusys_pclk_pd, 0x208, BIT(0), 0);
838 static CCU_GATE(CLK_SRAM0, sram0_clk, "sram0", axi_aclk_pd, 0x20c, BIT(4), 0);
839 static CCU_GATE(CLK_SRAM1, sram1_clk, "sram1", axi_aclk_pd, 0x20c, BIT(3), 0);
840 static CCU_GATE(CLK_SRAM2, sram2_clk, "sram2", axi_aclk_pd, 0x20c, BIT(2), 0);
841 static CCU_GATE(CLK_SRAM3, sram3_clk, "sram3", axi_aclk_pd, 0x20c, BIT(1), 0);
844 &gmac_pll_clk.common.hw, 10, 1, 0);
848 { .index = 0 },
852 .mux = TH_CCU_ARG(0, 1),
855 .cfg0 = 0x210,
859 0),
984 base = devm_platform_ioremap_resource(pdev, 0); in th1520_clk_probe()
992 for (i = 0; i < ARRAY_SIZE(th1520_pll_clks); i++) { in th1520_clk_probe()
1004 for (i = 0; i < ARRAY_SIZE(th1520_div_clks); i++) { in th1520_clk_probe()
1016 for (i = 0; i < ARRAY_SIZE(th1520_mux_clks); i++) { in th1520_clk_probe()
1025 0, in th1520_clk_probe()
1029 0, NULL, NULL); in th1520_clk_probe()
1036 for (i = 0; i < ARRAY_SIZE(th1520_gate_clks); i++) { in th1520_clk_probe()
1044 0, base + cg->common.cfg0, in th1520_clk_probe()
1045 ffs(cg->enable) - 1, 0, NULL); in th1520_clk_probe()
1066 return 0; in th1520_clk_probe()