785 	if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) {  in tegra210_pllcx_set_defaults()
834 	u32 val = readl_relaxed(clk_base + plla->params->base_reg);  in tegra210_plla_set_defaults()
871 	writel_relaxed(val, clk_base + plla->params->base_reg);  in tegra210_plla_set_defaults()
890 	if (readl_relaxed(clk_base + plld->params->base_reg) &  in tegra210_plld_set_defaults()
940 	u32 val = readl_relaxed(clk_base + plldss->params->base_reg);  in plldss_defaults()
991 					plldss->params->base_reg);  in plldss_defaults()
1006 	writel_relaxed(val, clk_base + plldss->params->base_reg);  in plldss_defaults()
1059 	u32 val = readl_relaxed(clk_base + pllre->params->base_reg);  in tegra210_pllre_set_defaults()
1103 	writel_relaxed(val, clk_base + pllre->params->base_reg);  in tegra210_pllre_set_defaults()
1188 	if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {  in tegra210_pllx_set_defaults()
1237 	u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg);  in tegra210_pllmb_set_defaults()
1298 	u32 val = readl_relaxed(clk_base + pllp->params->base_reg);  in tegra210_pllp_set_defaults()
1361 	u32 val = readl_relaxed(clk_base + pllu->base_reg);  in tegra210_pllu_set_defaults()
1452 	base = readl_relaxed(clk_base + pllx->params->base_reg) &  in tegra210_pllx_dyn_ramp()
1455 	writel_relaxed(base, clk_base + pllx->params->base_reg);  in tegra210_pllx_dyn_ramp()
1660 	.base_reg = PLLX_BASE,
1711 	.base_reg = PLLC_BASE,
1750 	.base_reg = PLLC2_BASE,
1780 	.base_reg = PLLC3_BASE,
1845 	.base_reg = PLLC4_BASE,
1899 	.base_reg = PLLM_BASE,
1926 	.base_reg = PLLMB_BASE,
1971 	.base_reg = PLLE_BASE,
2008 	.base_reg = PLLRE_BASE,
2047 	.base_reg = PLLP_BASE,
2070 	.base_reg = PLLA1_BASE,
2120 	.base_reg = PLLA_BASE,
2167 	.base_reg = PLLD_BASE,
2206 	.base_reg = PLLD2_BASE,
2250 	.base_reg = PLLDP_BASE,
2302 	.base_reg = PLLU_BASE,