clk/tegra/clk-tegra20.c

1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/tegra20-car.h>
18 #include "clk-id.h"
444 	{ .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
445 	{ .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
446 	{ .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
447 	{ .dev_id = "timer", .dt_id = TEGRA20_CLK_TIMER },
448 	{ .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC },
450 	{ .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP },
451 	{ .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA },
452 	{ .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA20_CLK_BSEV },
454 	{ .dev_id = "fsl-tegra-udc", .dt_id = TEGRA20_CLK_USBD },
455 	{ .dev_id = "tegra-ehci.1", .dt_id = TEGRA20_CLK_USB2 },
456 	{ .dev_id = "tegra-ehci.2", .dt_id = TEGRA20_CLK_USB3 },
467 	{ .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 },
468 	{ .dev_id = "tegra20-i2s.1", .dt_id = TEGRA20_CLK_I2S2 },
469 	{ .con_id = "spdif_out", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_OUT },
470 	{ .con_id = "spdif_in", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_IN },
492 	{ .dev_id = "tegra-nor", .dt_id = TEGRA20_CLK_NOR },
493 	{ .dev_id = "sdhci-tegra.0", .dt_id = TEGRA20_CLK_SDMMC1 },
494 	{ .dev_id = "sdhci-tegra.1", .dt_id = TEGRA20_CLK_SDMMC2 },
495 	{ .dev_id = "sdhci-tegra.2", .dt_id = TEGRA20_CLK_SDMMC3 },
496 	{ .dev_id = "sdhci-tegra.3", .dt_id = TEGRA20_CLK_SDMMC4 },
502 	{ .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 },
503 	{ .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 },
504 	{ .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 },
505 	{ .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC },
506 	{ .dev_id = "tegra-pwm", .dt_id = TEGRA20_CLK_PWM },
840 		clks[data->clk_id] = clk;  in tegra20_periph_clk_init()
845 		clk = tegra_clk_register_periph_nodiv(data->name,  in tegra20_periph_clk_init()
846 					data->p.parent_names,  in tegra20_periph_clk_init()
847 					data->num_parents, &data->periph,  in tegra20_periph_clk_init()
848 					clk_base, data->offset);  in tegra20_periph_clk_init()
849 		clks[data->clk_id] = clk;  in tegra20_periph_clk_init()
875 /* Tegra20 CPU clock and reset control functions */
1057 	TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD,    "utmip-pad",     NULL),
1058 	TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD,    "tegra-ehci.0",  NULL),
1059 	TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD,    "tegra-otg",     NULL),
1066 	{ .compatible = "nvidia,tegra20-pmc" },
1080 	 * Timer clocks are needed early, the rest of the clocks shouldn't be  in tegra20_clk_src_onecell_get()
1083 	if (clkspec->args[0] != TEGRA20_CLK_RTC &&  in tegra20_clk_src_onecell_get()
1084 	    clkspec->args[0] != TEGRA20_CLK_TWD &&  in tegra20_clk_src_onecell_get()
1085 	    clkspec->args[0] != TEGRA20_CLK_TIMER &&  in tegra20_clk_src_onecell_get()
1087 		return ERR_PTR(-EPROBE_DEFER);  in tegra20_clk_src_onecell_get()
1096 	 * Tegra20 CDEV1 and CDEV2 clocks are a bit special case, their parent  in tegra20_clk_src_onecell_get()
1102 	if (clkspec->args[0] == TEGRA20_CLK_CDEV1 ||  in tegra20_clk_src_onecell_get()
1103 	    clkspec->args[0] == TEGRA20_CLK_CDEV2) {  in tegra20_clk_src_onecell_get()
1106 			return ERR_PTR(-EPROBE_DEFER);  in tegra20_clk_src_onecell_get()
1109 	if (clkspec->args[0] == TEGRA20_CLK_EMC) {  in tegra20_clk_src_onecell_get()
1111 			return ERR_PTR(-EPROBE_DEFER);  in tegra20_clk_src_onecell_get()
1159 CLK_OF_DECLARE_DRIVER(tegra20, "nvidia,tegra20-car", tegra20_clock_init);
1188 	{ .compatible = "nvidia,tegra20-car" },
1194 		.name = "tegra20-car",