1 // SPDX-License-Identifier: GPL-2.0-only
3  * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
29 #define CLK_SOURCE_EMC 0x19c
31 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
32 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff
37 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7
47  * List of clock sources for various parents the EMC clock can have.
53 #define EMC_SRC_PLL_M 0
79 	struct tegra_emc *emc;  member
82 	struct emc_timing *timings;  member
105 	val = readl(tegra->clk_regs + CLK_SOURCE_EMC);  in emc_recalc_rate()
113  * safer since things have EMC rate floors. Also don't touch parent_rate
125 	for (k = 0; k < tegra->num_timings; k++) {  in emc_determine_rate()
126 		if (tegra->timings[k].ram_code == ram_code)  in emc_determine_rate()
130 	for (t = k; t < tegra->num_timings; t++) {  in emc_determine_rate()
131 		if (tegra->timings[t].ram_code != ram_code)  in emc_determine_rate()
136 		timing = tegra->timings + i;  in emc_determine_rate()
138 		if (timing->rate < req->rate && i != t - 1)  in emc_determine_rate()
141 		if (timing->rate > req->max_rate) {  in emc_determine_rate()
143 			req->rate = tegra->timings[i - 1].rate;  in emc_determine_rate()
144 			return 0;  in emc_determine_rate()
147 		if (timing->rate < req->min_rate)  in emc_determine_rate()
150 		req->rate = timing->rate;  in emc_determine_rate()
151 		return 0;  in emc_determine_rate()
155 		req->rate = timing->rate;  in emc_determine_rate()
156 		return 0;  in emc_determine_rate()
159 	req->rate = clk_hw_get_rate(hw);  in emc_determine_rate()
160 	return 0;  in emc_determine_rate()
170 	val = readl(tegra->clk_regs + CLK_SOURCE_EMC);  in emc_get_parent()
180 	if (tegra->emc)  in emc_ensure_emc_driver()
181 		return tegra->emc;  in emc_ensure_emc_driver()
183 	if (!tegra->prepare_timing_change || !tegra->complete_timing_change)  in emc_ensure_emc_driver()
186 	if (!tegra->emc_node)  in emc_ensure_emc_driver()
189 	pdev = of_find_device_by_node(tegra->emc_node);  in emc_ensure_emc_driver()
196 	of_node_put(tegra->emc_node);  in emc_ensure_emc_driver()
197 	tegra->emc_node = NULL;  in emc_ensure_emc_driver()
199 	tegra->emc = platform_get_drvdata(pdev);  in emc_ensure_emc_driver()
200 	if (!tegra->emc) {  in emc_ensure_emc_driver()
201 		put_device(&pdev->dev);  in emc_ensure_emc_driver()
202 		pr_err("%s: cannot find EMC driver\n", __func__);  in emc_ensure_emc_driver()
206 	return tegra->emc;  in emc_ensure_emc_driver()
215 	unsigned long flags = 0;  in emc_set_timing()
216 	struct tegra_emc *emc = emc_ensure_emc_driver(tegra);  in emc_set_timing()  local
218 	if (!emc)  in emc_set_timing()
219 		return -ENOENT;  in emc_set_timing()
221 	pr_debug("going to rate %ld prate %ld p %s\n", timing->rate,  in emc_set_timing()
222 		 timing->parent_rate, __clk_get_name(timing->parent));  in emc_set_timing()
224 	if (emc_get_parent(&tegra->hw) == timing->parent_index &&  in emc_set_timing()
225 	    clk_get_rate(timing->parent) != timing->parent_rate) {  in emc_set_timing()
227 			  __clk_get_name(timing->parent),  in emc_set_timing()
228 			  clk_get_rate(timing->parent),  in emc_set_timing()
229 			  timing->parent_rate);  in emc_set_timing()
230 		return -EINVAL;  in emc_set_timing()
233 	tegra->changing_timing = true;  in emc_set_timing()
235 	err = clk_set_rate(timing->parent, timing->parent_rate);  in emc_set_timing()
238 		       __clk_get_name(timing->parent), timing->parent_rate,  in emc_set_timing()
244 	err = clk_prepare_enable(timing->parent);  in emc_set_timing()
250 	div = timing->parent_rate / (timing->rate / 2) - 2;  in emc_set_timing()
252 	err = tegra->prepare_timing_change(emc, timing->rate);  in emc_set_timing()
254 		clk_disable_unprepare(timing->parent);  in emc_set_timing()
258 	spin_lock_irqsave(tegra->lock, flags);  in emc_set_timing()
260 	car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC);  in emc_set_timing()
262 	car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_SRC(~0);  in emc_set_timing()
263 	car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);  in emc_set_timing()
265 	car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(~0);  in emc_set_timing()
268 	writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC);  in emc_set_timing()
270 	spin_unlock_irqrestore(tegra->lock, flags);  in emc_set_timing()
272 	tegra->complete_timing_change(emc, timing->rate);  in emc_set_timing()
274 	clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));  in emc_set_timing()
275 	clk_disable_unprepare(tegra->prev_parent);  in emc_set_timing()
277 	tegra->prev_parent = timing->parent;  in emc_set_timing()
278 	tegra->changing_timing = false;  in emc_set_timing()
280 	return 0;  in emc_set_timing()
285  * two timings with the same clock source has been requested. First try to
296 	for (i = timing_index+1; i < tegra->num_timings; i++) {  in get_backup_timing()
297 		timing = tegra->timings + i;  in get_backup_timing()
298 		if (timing->ram_code != ram_code)  in get_backup_timing()
301 		if (emc_parent_clk_sources[timing->parent_index] !=  in get_backup_timing()
303 		      tegra->timings[timing_index].parent_index])  in get_backup_timing()
307 	for (i = timing_index-1; i >= 0; --i) {  in get_backup_timing()
308 		timing = tegra->timings + i;  in get_backup_timing()
309 		if (timing->ram_code != ram_code)  in get_backup_timing()
312 		if (emc_parent_clk_sources[timing->parent_index] !=  in get_backup_timing()
314 		      tegra->timings[timing_index].parent_index])  in get_backup_timing()
332 		return 0;  in emc_set_rate()
339 	if (tegra->changing_timing)  in emc_set_rate()
340 		return 0;  in emc_set_rate()
342 	for (i = 0; i < tegra->num_timings; i++) {  in emc_set_rate()
343 		if (tegra->timings[i].rate == rate &&  in emc_set_rate()
344 		    tegra->timings[i].ram_code == ram_code) {  in emc_set_rate()
345 			timing = tegra->timings + i;  in emc_set_rate()
351 		pr_err("cannot switch to rate %ld without emc table\n", rate);  in emc_set_rate()
352 		return -EINVAL;  in emc_set_rate()
356 	    emc_parent_clk_sources[timing->parent_index] &&  in emc_set_rate()
357 	    clk_get_rate(timing->parent) != timing->parent_rate) {  in emc_set_rate()
368 			return -EINVAL;  in emc_set_rate()
372 			 backup_timing->rate, rate);  in emc_set_rate()
393 	err = of_property_read_u32(node, "clock-frequency", &tmp);  in load_one_timing_from_dt()
399 	timing->rate = tmp;  in load_one_timing_from_dt()
401 	err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp);  in load_one_timing_from_dt()
407 	timing->parent_rate = tmp;  in load_one_timing_from_dt()
409 	timing->parent = of_clk_get_by_name(node, "emc-parent");  in load_one_timing_from_dt()
410 	if (IS_ERR(timing->parent)) {  in load_one_timing_from_dt()
412 		return PTR_ERR(timing->parent);  in load_one_timing_from_dt()
415 	timing->parent_index = 0xff;  in load_one_timing_from_dt()
417 			 __clk_get_name(timing->parent));  in load_one_timing_from_dt()
418 	if (i < 0) {  in load_one_timing_from_dt()
420 		       node, __clk_get_name(timing->parent));  in load_one_timing_from_dt()
421 		clk_put(timing->parent);  in load_one_timing_from_dt()
422 		return -EINVAL;  in load_one_timing_from_dt()
425 	timing->parent_index = i;  in load_one_timing_from_dt()
426 	return 0;  in load_one_timing_from_dt()
434 	if (a->rate < b->rate)  in cmp_timings()
435 		return -1;  in cmp_timings()
436 	else if (a->rate == b->rate)  in cmp_timings()
437 		return 0;  in cmp_timings()
449 	int i = 0, err;  in load_timings_from_dt()
452 	size = (tegra->num_timings + child_count) * sizeof(struct emc_timing);  in load_timings_from_dt()
454 	tegra->timings = krealloc(tegra->timings, size, GFP_KERNEL);  in load_timings_from_dt()
455 	if (!tegra->timings)  in load_timings_from_dt()
456 		return -ENOMEM;  in load_timings_from_dt()
458 	timings_ptr = tegra->timings + tegra->num_timings;  in load_timings_from_dt()
459 	tegra->num_timings += child_count;  in load_timings_from_dt()
467 			kfree(tegra->timings);  in load_timings_from_dt()
471 		timing->ram_code = ram_code;  in load_timings_from_dt()
477 	return 0;  in load_timings_from_dt()
499 		return ERR_PTR(-ENOMEM);  in tegra124_clk_register_emc()
501 	tegra->clk_regs = base;  in tegra124_clk_register_emc()
502 	tegra->lock = lock;  in tegra124_clk_register_emc()
504 	tegra->num_timings = 0;  in tegra124_clk_register_emc()
507 		err = of_property_read_u32(node, "nvidia,ram-code",  in tegra124_clk_register_emc()
513 		 * Store timings for all ram codes as we cannot read the  in tegra124_clk_register_emc()
524 	if (tegra->num_timings == 0)  in tegra124_clk_register_emc()
525 		pr_warn("%s: no memory timings registered\n", __func__);  in tegra124_clk_register_emc()
527 	tegra->emc_node = of_parse_phandle(np,  in tegra124_clk_register_emc()
528 			"nvidia,external-memory-controller", 0);  in tegra124_clk_register_emc()
529 	if (!tegra->emc_node)  in tegra124_clk_register_emc()
530 		pr_warn("%s: couldn't find node for EMC driver\n", __func__);  in tegra124_clk_register_emc()
532 	init.name = "emc";  in tegra124_clk_register_emc()
538 	tegra->hw.init = &init;  in tegra124_clk_register_emc()
540 	clk = clk_register(NULL, &tegra->hw);  in tegra124_clk_register_emc()
544 	tegra->prev_parent = clk_hw_get_parent_by_index(  in tegra124_clk_register_emc()
545 		&tegra->hw, emc_get_parent(&tegra->hw))->clk;  in tegra124_clk_register_emc()
546 	tegra->changing_timing = false;  in tegra124_clk_register_emc()
548 	/* Allow debugging tools to see the EMC clock */  in tegra124_clk_register_emc()
549 	clk_register_clkdev(clk, "emc", "tegra-clk-debug");  in tegra124_clk_register_emc()
557 	struct clk *clk = __clk_lookup("emc");  in tegra124_clk_set_emc_callbacks()
565 		tegra->prepare_timing_change = prep_cb;  in tegra124_clk_set_emc_callbacks()
566 		tegra->complete_timing_change = complete_cb;  in tegra124_clk_set_emc_callbacks()
575 	return tegra->prepare_timing_change && tegra->complete_timing_change;  in tegra124_clk_emc_driver_available()