48  * When we change the timing to a timing with a parent that has the same
50  * timing that has a different clock source.
120 	struct emc_timing *timing = NULL;  in emc_determine_rate()  local
136 		timing = tegra->timings + i;  in emc_determine_rate()
138 		if (timing->rate < req->rate && i != t - 1)  in emc_determine_rate()
141 		if (timing->rate > req->max_rate) {  in emc_determine_rate()
147 		if (timing->rate < req->min_rate)  in emc_determine_rate()
150 		req->rate = timing->rate;  in emc_determine_rate()
154 	if (timing) {  in emc_determine_rate()
155 		req->rate = timing->rate;  in emc_determine_rate()
210 			  struct emc_timing *timing)  in emc_set_timing()  argument
221 	pr_debug("going to rate %ld prate %ld p %s\n", timing->rate,  in emc_set_timing()
222 		 timing->parent_rate, __clk_get_name(timing->parent));  in emc_set_timing()
224 	if (emc_get_parent(&tegra->hw) == timing->parent_index &&  in emc_set_timing()
225 	    clk_get_rate(timing->parent) != timing->parent_rate) {  in emc_set_timing()
227 			  __clk_get_name(timing->parent),  in emc_set_timing()
228 			  clk_get_rate(timing->parent),  in emc_set_timing()
229 			  timing->parent_rate);  in emc_set_timing()
235 	err = clk_set_rate(timing->parent, timing->parent_rate);  in emc_set_timing()
238 		       __clk_get_name(timing->parent), timing->parent_rate,  in emc_set_timing()
244 	err = clk_prepare_enable(timing->parent);  in emc_set_timing()
250 	div = timing->parent_rate / (timing->rate / 2) - 2;  in emc_set_timing()
252 	err = tegra->prepare_timing_change(emc, timing->rate);  in emc_set_timing()
254 		clk_disable_unprepare(timing->parent);  in emc_set_timing()
263 	car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);  in emc_set_timing()
272 	tegra->complete_timing_change(emc, timing->rate);  in emc_set_timing()
274 	clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));  in emc_set_timing()
277 	tegra->prev_parent = timing->parent;  in emc_set_timing()
284  * Get backup timing to use as an intermediate step when a change between
286  * find a timing with a higher clock rate to avoid a rate below any set rate
294 	struct emc_timing *timing;  in get_backup_timing()  local
297 		timing = tegra->timings + i;  in get_backup_timing()
298 		if (timing->ram_code != ram_code)  in get_backup_timing()
301 		if (emc_parent_clk_sources[timing->parent_index] !=  in get_backup_timing()
304 			return timing;  in get_backup_timing()
308 		timing = tegra->timings + i;  in get_backup_timing()
309 		if (timing->ram_code != ram_code)  in get_backup_timing()
312 		if (emc_parent_clk_sources[timing->parent_index] !=  in get_backup_timing()
315 			return timing;  in get_backup_timing()
325 	struct emc_timing *timing = NULL;  in emc_set_rate()  local
345 			timing = tegra->timings + i;  in emc_set_rate()
350 	if (!timing) {  in emc_set_rate()
356 	    emc_parent_clk_sources[timing->parent_index] &&  in emc_set_rate()
357 	    clk_get_rate(timing->parent) != timing->parent_rate) {  in emc_set_rate()
367 			pr_err("cannot find backup timing\n");  in emc_set_rate()
376 			pr_err("cannot set backup timing: %d\n", err);  in emc_set_rate()
381 	return emc_set_timing(tegra, timing);  in emc_set_rate()
387 				   struct emc_timing *timing,  in load_one_timing_from_dt()  argument
395 		pr_err("timing %pOF: failed to read rate\n", node);  in load_one_timing_from_dt()
399 	timing->rate = tmp;  in load_one_timing_from_dt()
403 		pr_err("timing %pOF: failed to read parent rate\n", node);  in load_one_timing_from_dt()
407 	timing->parent_rate = tmp;  in load_one_timing_from_dt()
409 	timing->parent = of_clk_get_by_name(node, "emc-parent");  in load_one_timing_from_dt()
410 	if (IS_ERR(timing->parent)) {  in load_one_timing_from_dt()
411 		pr_err("timing %pOF: failed to get parent clock\n", node);  in load_one_timing_from_dt()
412 		return PTR_ERR(timing->parent);  in load_one_timing_from_dt()
415 	timing->parent_index = 0xff;  in load_one_timing_from_dt()
417 			 __clk_get_name(timing->parent));  in load_one_timing_from_dt()
419 		pr_err("timing %pOF: %s is not a valid parent\n",  in load_one_timing_from_dt()
420 		       node, __clk_get_name(timing->parent));  in load_one_timing_from_dt()
421 		clk_put(timing->parent);  in load_one_timing_from_dt()
425 	timing->parent_index = i;  in load_one_timing_from_dt()
462 		struct emc_timing *timing = timings_ptr + (i++);  in load_timings_from_dt()  local
464 		err = load_one_timing_from_dt(tegra, timing, child);  in load_timings_from_dt()
471 		timing->ram_code = ram_code;  in load_timings_from_dt()