Lines Matching refs:TEGRA114_CLK_PLL_P
748 [tegra_clk_pll_p] = { .dt_id = TEGRA114_CLK_PLL_P, .present = true },
819 { .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P },
1135 { TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0 },
1136 { TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0 },
1137 { TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0 },
1138 { TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0 },
1146 { TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0 },
1147 { TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1 },
1148 { TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1 },
1149 { TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0 },
1150 { TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0 },
1153 { TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0 },
1154 { TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0 },
1159 { TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },
1160 { TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },
1161 { TEGRA114_CLK_VDE, TEGRA114_CLK_PLL_P, 408000000, 0 },
1169 { TEGRA114_CLK_PWM, TEGRA114_CLK_PLL_P, 408000000, 0 },