Lines Matching +full:super +full:- +full:set
1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
28 #define super_state_to_src_shift(m, s) ((m->width * s))
29 #define super_state_to_src_mask(m) (((1 << m->width) - 1))
40 val = readl_relaxed(mux->reg); in clk_super_get_parent()
53 * If LP_DIV2_BYPASS is not set and PLLX is current parent then in clk_super_get_parent()
56 if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) && in clk_super_get_parent()
57 (source == mux->pllx_index)) in clk_super_get_parent()
58 source = mux->div2_index; in clk_super_get_parent()
71 if (mux->lock) in clk_super_set_parent()
72 spin_lock_irqsave(mux->lock, flags); in clk_super_set_parent()
74 val = readl_relaxed(mux->reg); in clk_super_set_parent()
83 * For LP mode super-clock switch between PLLX direct in clk_super_set_parent()
84 * and divided-by-2 outputs is allowed only when other in clk_super_set_parent()
87 if ((mux->flags & TEGRA_DIVIDER_2) && ((index == mux->div2_index) || in clk_super_set_parent()
88 (index == mux->pllx_index))) { in clk_super_set_parent()
90 if ((parent_index == mux->div2_index) || in clk_super_set_parent()
91 (parent_index == mux->pllx_index)) { in clk_super_set_parent()
92 err = -EINVAL; in clk_super_set_parent()
97 writel_relaxed(val, mux->reg); in clk_super_set_parent()
100 if (index == mux->div2_index) in clk_super_set_parent()
101 index = mux->pllx_index; in clk_super_set_parent()
105 if ((mux->flags & TEGRA210_CPU_CLK) && in clk_super_set_parent()
112 writel_relaxed(val, mux->reg); in clk_super_set_parent()
116 if ((mux->flags & TEGRA210_CPU_CLK) && in clk_super_set_parent()
121 if (mux->lock) in clk_super_set_parent()
122 spin_unlock_irqrestore(mux->lock, flags); in clk_super_set_parent()
148 struct tegra_clk_super_mux *super = to_clk_super_mux(hw); in clk_super_determine_rate() local
149 struct clk_hw *div_hw = &super->frac_div.hw; in clk_super_determine_rate()
154 rate = super->div_ops->round_rate(div_hw, req->rate, in clk_super_determine_rate()
155 &req->best_parent_rate); in clk_super_determine_rate()
159 req->rate = rate; in clk_super_determine_rate()
166 struct tegra_clk_super_mux *super = to_clk_super_mux(hw); in clk_super_recalc_rate() local
167 struct clk_hw *div_hw = &super->frac_div.hw; in clk_super_recalc_rate()
171 return super->div_ops->recalc_rate(div_hw, parent_rate); in clk_super_recalc_rate()
177 struct tegra_clk_super_mux *super = to_clk_super_mux(hw); in clk_super_set_rate() local
178 struct clk_hw *div_hw = &super->frac_div.hw; in clk_super_set_rate()
182 return super->div_ops->set_rate(div_hw, rate, parent_rate); in clk_super_set_rate()
187 struct tegra_clk_super_mux *super = to_clk_super_mux(hw); in clk_super_restore_context() local
188 struct clk_hw *div_hw = &super->frac_div.hw; in clk_super_restore_context()
195 super->div_ops->restore_context(div_hw); in clk_super_restore_context()
213 struct tegra_clk_super_mux *super; in tegra_clk_register_super_mux() local
217 super = kzalloc(sizeof(*super), GFP_KERNEL); in tegra_clk_register_super_mux()
218 if (!super) in tegra_clk_register_super_mux()
219 return ERR_PTR(-ENOMEM); in tegra_clk_register_super_mux()
227 super->reg = reg; in tegra_clk_register_super_mux()
228 super->pllx_index = pllx_index; in tegra_clk_register_super_mux()
229 super->div2_index = div2_index; in tegra_clk_register_super_mux()
230 super->lock = lock; in tegra_clk_register_super_mux()
231 super->width = width; in tegra_clk_register_super_mux()
232 super->flags = clk_super_flags; in tegra_clk_register_super_mux()
235 super->hw.init = &init; in tegra_clk_register_super_mux()
237 clk = tegra_clk_dev_register(&super->hw); in tegra_clk_register_super_mux()
239 kfree(super); in tegra_clk_register_super_mux()
249 struct tegra_clk_super_mux *super; in tegra_clk_register_super_clk() local
253 super = kzalloc(sizeof(*super), GFP_KERNEL); in tegra_clk_register_super_clk()
254 if (!super) in tegra_clk_register_super_clk()
255 return ERR_PTR(-ENOMEM); in tegra_clk_register_super_clk()
263 super->reg = reg; in tegra_clk_register_super_clk()
264 super->lock = lock; in tegra_clk_register_super_clk()
265 super->width = 4; in tegra_clk_register_super_clk()
266 super->flags = clk_super_flags; in tegra_clk_register_super_clk()
267 super->frac_div.reg = reg + 4; in tegra_clk_register_super_clk()
268 super->frac_div.shift = 16; in tegra_clk_register_super_clk()
269 super->frac_div.width = 8; in tegra_clk_register_super_clk()
270 super->frac_div.frac_width = 1; in tegra_clk_register_super_clk()
271 super->frac_div.lock = lock; in tegra_clk_register_super_clk()
272 super->div_ops = &tegra_clk_frac_div_ops; in tegra_clk_register_super_clk()
275 super->hw.init = &init; in tegra_clk_register_super_clk()
277 clk = clk_register(NULL, &super->hw); in tegra_clk_register_super_clk()
279 kfree(super); in tegra_clk_register_super_clk()