clk/tegra/clk-pll.c

252 #define divm_shift(p) (p)->params->div_nmp->divm_shift  macro
256 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
270 	.divm_shift = PLL_BASE_DIVM_SHIFT,
682 		val |= (cfg->m << divm_shift(pll)) |  in _update_pll_mnp()
713 		cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);  in _get_pll_mnp()
990 		val |= sel.m << divm_shift(pll);  in clk_plle_enable()
1026 	divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));  in clk_plle_recalc_rate()
1653 	val |= sel.m << divm_shift(pll);  in clk_plle_tegra114_enable()
1945 	.divm_shift = PLLE_BASE_DIVM_SHIFT,
2136 		val = m << divm_shift(pll);  in tegra_clk_register_pllre()
2493 	val |= sel.m << divm_shift(pll);  in clk_plle_tegra210_enable()