Lines Matching full:pll
276 static void clk_pll_enable_lock(struct tegra_clk_pll *pll) in clk_pll_enable_lock() argument
280 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) in clk_pll_enable_lock()
283 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) in clk_pll_enable_lock()
286 val = pll_readl_misc(pll); in clk_pll_enable_lock()
287 val |= BIT(pll->params->lock_enable_bit_idx); in clk_pll_enable_lock()
288 pll_writel_misc(val, pll); in clk_pll_enable_lock()
291 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) in clk_pll_wait_for_lock() argument
297 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { in clk_pll_wait_for_lock()
298 udelay(pll->params->lock_delay); in clk_pll_wait_for_lock()
302 lock_addr = pll->clk_base; in clk_pll_wait_for_lock()
303 if (pll->params->flags & TEGRA_PLL_LOCK_MISC) in clk_pll_wait_for_lock()
304 lock_addr += pll->params->misc_reg; in clk_pll_wait_for_lock()
306 lock_addr += pll->params->base_reg; in clk_pll_wait_for_lock()
308 lock_mask = pll->params->lock_mask; in clk_pll_wait_for_lock()
310 for (i = 0; i < pll->params->lock_delay; i++) { in clk_pll_wait_for_lock()
319 pr_err("%s: Timed out waiting for pll %s lock\n", __func__, in clk_pll_wait_for_lock()
320 clk_hw_get_name(&pll->hw)); in clk_pll_wait_for_lock()
325 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll) in tegra_pll_wait_for_lock() argument
327 return clk_pll_wait_for_lock(pll); in tegra_pll_wait_for_lock()
330 static bool pllm_clk_is_gated_by_pmc(struct tegra_clk_pll *pll) in pllm_clk_is_gated_by_pmc() argument
332 u32 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); in pllm_clk_is_gated_by_pmc()
340 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pll_is_enabled() local
348 if ((pll->params->flags & TEGRA_PLLM) && pllm_clk_is_gated_by_pmc(pll)) in clk_pll_is_enabled()
351 val = pll_readl_base(pll); in clk_pll_is_enabled()
358 struct tegra_clk_pll *pll = to_clk_pll(hw); in _clk_pll_enable() local
361 if (pll->params->iddq_reg) { in _clk_pll_enable()
362 val = pll_readl(pll->params->iddq_reg, pll); in _clk_pll_enable()
363 val &= ~BIT(pll->params->iddq_bit_idx); in _clk_pll_enable()
364 pll_writel(val, pll->params->iddq_reg, pll); in _clk_pll_enable()
368 if (pll->params->reset_reg) { in _clk_pll_enable()
369 val = pll_readl(pll->params->reset_reg, pll); in _clk_pll_enable()
370 val &= ~BIT(pll->params->reset_bit_idx); in _clk_pll_enable()
371 pll_writel(val, pll->params->reset_reg, pll); in _clk_pll_enable()
374 clk_pll_enable_lock(pll); in _clk_pll_enable()
376 val = pll_readl_base(pll); in _clk_pll_enable()
377 if (pll->params->flags & TEGRA_PLL_BYPASS) in _clk_pll_enable()
380 pll_writel_base(val, pll); in _clk_pll_enable()
382 if (pll->params->flags & TEGRA_PLLM) { in _clk_pll_enable()
383 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_enable()
385 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_enable()
391 struct tegra_clk_pll *pll = to_clk_pll(hw); in _clk_pll_disable() local
394 val = pll_readl_base(pll); in _clk_pll_disable()
395 if (pll->params->flags & TEGRA_PLL_BYPASS) in _clk_pll_disable()
398 pll_writel_base(val, pll); in _clk_pll_disable()
400 if (pll->params->flags & TEGRA_PLLM) { in _clk_pll_disable()
401 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_disable()
403 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_disable()
406 if (pll->params->reset_reg) { in _clk_pll_disable()
407 val = pll_readl(pll->params->reset_reg, pll); in _clk_pll_disable()
408 val |= BIT(pll->params->reset_bit_idx); in _clk_pll_disable()
409 pll_writel(val, pll->params->reset_reg, pll); in _clk_pll_disable()
412 if (pll->params->iddq_reg) { in _clk_pll_disable()
413 val = pll_readl(pll->params->iddq_reg, pll); in _clk_pll_disable()
414 val |= BIT(pll->params->iddq_bit_idx); in _clk_pll_disable()
415 pll_writel(val, pll->params->iddq_reg, pll); in _clk_pll_disable()
420 static void pll_clk_start_ss(struct tegra_clk_pll *pll) in pll_clk_start_ss() argument
422 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) { in pll_clk_start_ss()
423 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll); in pll_clk_start_ss()
425 val |= pll->params->ssc_ctrl_en_mask; in pll_clk_start_ss()
426 pll_writel(val, pll->params->ssc_ctrl_reg, pll); in pll_clk_start_ss()
430 static void pll_clk_stop_ss(struct tegra_clk_pll *pll) in pll_clk_stop_ss() argument
432 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) { in pll_clk_stop_ss()
433 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll); in pll_clk_stop_ss()
435 val &= ~pll->params->ssc_ctrl_en_mask; in pll_clk_stop_ss()
436 pll_writel(val, pll->params->ssc_ctrl_reg, pll); in pll_clk_stop_ss()
442 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
449 if (pll->lock) in clk_pll_enable()
450 spin_lock_irqsave(pll->lock, flags); in clk_pll_enable()
454 ret = clk_pll_wait_for_lock(pll); in clk_pll_enable()
456 pll_clk_start_ss(pll); in clk_pll_enable()
458 if (pll->lock) in clk_pll_enable()
459 spin_unlock_irqrestore(pll->lock, flags); in clk_pll_enable()
466 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pll_disable() local
469 if (pll->lock) in clk_pll_disable()
470 spin_lock_irqsave(pll->lock, flags); in clk_pll_disable()
472 pll_clk_stop_ss(pll); in clk_pll_disable()
476 if (pll->lock) in clk_pll_disable()
477 spin_unlock_irqrestore(pll->lock, flags); in clk_pll_disable()
482 struct tegra_clk_pll *pll = to_clk_pll(hw); in _p_div_to_hw() local
483 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; in _p_div_to_hw()
496 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div) in tegra_pll_p_div_to_hw() argument
498 return _p_div_to_hw(&pll->hw, p_div); in tegra_pll_p_div_to_hw()
503 struct tegra_clk_pll *pll = to_clk_pll(hw); in _hw_to_p_div() local
504 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; in _hw_to_p_div()
522 struct tegra_clk_pll *pll = to_clk_pll(hw); in _get_table_rate() local
526 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) in _get_table_rate()
534 if (pll->params->pdiv_tohw) { in _get_table_rate()
556 struct tegra_clk_pll *pll = to_clk_pll(hw); in _calc_rate() local
598 if (cfg->m == 0 || cfg->m > divm_max(pll) || in _calc_rate()
599 cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) || in _calc_rate()
600 cfg->output_rate > pll->params->vco_max) { in _calc_rate()
607 if (pll->params->pdiv_tohw) { in _calc_rate()
621 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
630 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pll_set_sdm_data() local
634 if (!pll->params->sdm_din_reg) in clk_pll_set_sdm_data()
638 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll)); in clk_pll_set_sdm_data()
639 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll); in clk_pll_set_sdm_data()
640 pll_writel_sdm_din(val, pll); in clk_pll_set_sdm_data()
643 val = pll_readl_sdm_ctrl(pll); in clk_pll_set_sdm_data()
644 enabled = (val & sdm_en_mask(pll)); in clk_pll_set_sdm_data()
647 val &= ~pll->params->sdm_ctrl_en_mask; in clk_pll_set_sdm_data()
650 val |= pll->params->sdm_ctrl_en_mask; in clk_pll_set_sdm_data()
652 pll_writel_sdm_ctrl(val, pll); in clk_pll_set_sdm_data()
655 static void _update_pll_mnp(struct tegra_clk_pll *pll, in _update_pll_mnp() argument
659 struct tegra_clk_pll_params *params = pll->params; in _update_pll_mnp()
663 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & in _update_pll_mnp()
665 val = pll_override_readl(params->pmc_divp_reg, pll); in _update_pll_mnp()
666 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift); in _update_pll_mnp()
668 pll_override_writel(val, params->pmc_divp_reg, pll); in _update_pll_mnp()
670 val = pll_override_readl(params->pmc_divnm_reg, pll); in _update_pll_mnp()
671 val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) | in _update_pll_mnp()
672 (divn_mask(pll) << div_nmp->override_divn_shift)); in _update_pll_mnp()
675 pll_override_writel(val, params->pmc_divnm_reg, pll); in _update_pll_mnp()
677 val = pll_readl_base(pll); in _update_pll_mnp()
679 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) | in _update_pll_mnp()
680 divp_mask_shifted(pll)); in _update_pll_mnp()
682 val |= (cfg->m << divm_shift(pll)) | in _update_pll_mnp()
683 (cfg->n << divn_shift(pll)) | in _update_pll_mnp()
684 (cfg->p << divp_shift(pll)); in _update_pll_mnp()
686 pll_writel_base(val, pll); in _update_pll_mnp()
688 clk_pll_set_sdm_data(&pll->hw, cfg); in _update_pll_mnp()
692 static void _get_pll_mnp(struct tegra_clk_pll *pll, in _get_pll_mnp() argument
696 struct tegra_clk_pll_params *params = pll->params; in _get_pll_mnp()
702 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & in _get_pll_mnp()
704 val = pll_override_readl(params->pmc_divp_reg, pll); in _get_pll_mnp()
705 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll); in _get_pll_mnp()
707 val = pll_override_readl(params->pmc_divnm_reg, pll); in _get_pll_mnp()
708 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll); in _get_pll_mnp()
709 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll); in _get_pll_mnp()
711 val = pll_readl_base(pll); in _get_pll_mnp()
713 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll); in _get_pll_mnp()
714 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); in _get_pll_mnp()
715 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); in _get_pll_mnp()
717 if (pll->params->sdm_din_reg) { in _get_pll_mnp()
718 if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) { in _get_pll_mnp()
719 val = pll_readl_sdm_din(pll); in _get_pll_mnp()
720 val &= sdm_din_mask(pll); in _get_pll_mnp()
727 static void _update_pll_cpcon(struct tegra_clk_pll *pll, in _update_pll_cpcon() argument
733 val = pll_readl_misc(pll); in _update_pll_cpcon()
738 if (pll->params->flags & TEGRA_PLL_SET_LFCON) { in _update_pll_cpcon()
742 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) { in _update_pll_cpcon()
744 if (rate >= (pll->params->vco_max >> 1)) in _update_pll_cpcon()
748 pll_writel_misc(val, pll); in _update_pll_cpcon()
754 struct tegra_clk_pll *pll = to_clk_pll(hw); in _program_pll() local
760 if (state && pll->params->pre_rate_change) { in _program_pll()
761 ret = pll->params->pre_rate_change(); in _program_pll()
766 _get_pll_mnp(pll, &old_cfg); in _program_pll()
768 if (state && pll->params->defaults_set && pll->params->dyn_ramp && in _program_pll()
770 ret = pll->params->dyn_ramp(pll, cfg); in _program_pll()
776 pll_clk_stop_ss(pll); in _program_pll()
780 if (!pll->params->defaults_set && pll->params->set_defaults) in _program_pll()
781 pll->params->set_defaults(pll); in _program_pll()
783 _update_pll_mnp(pll, cfg); in _program_pll()
785 if (pll->params->flags & TEGRA_PLL_HAS_CPCON) in _program_pll()
786 _update_pll_cpcon(pll, cfg, rate); in _program_pll()
790 ret = clk_pll_wait_for_lock(pll); in _program_pll()
791 pll_clk_start_ss(pll); in _program_pll()
795 if (state && pll->params->post_rate_change) in _program_pll()
796 pll->params->post_rate_change(); in _program_pll()
804 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pll_set_rate() local
809 if (pll->params->flags & TEGRA_PLL_FIXED) { in clk_pll_set_rate()
810 if (rate != pll->params->fixed_rate) { in clk_pll_set_rate()
813 pll->params->fixed_rate, rate); in clk_pll_set_rate()
820 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) { in clk_pll_set_rate()
826 if (pll->lock) in clk_pll_set_rate()
827 spin_lock_irqsave(pll->lock, flags); in clk_pll_set_rate()
829 _get_pll_mnp(pll, &old_cfg); in clk_pll_set_rate()
830 if (pll->params->flags & TEGRA_PLL_VCO_OUT) in clk_pll_set_rate()
837 if (pll->lock) in clk_pll_set_rate()
838 spin_unlock_irqrestore(pll->lock, flags); in clk_pll_set_rate()
846 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pll_round_rate() local
849 if (pll->params->flags & TEGRA_PLL_FIXED) { in clk_pll_round_rate()
851 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) in clk_pll_round_rate()
853 return pll->params->fixed_rate; in clk_pll_round_rate()
857 pll->params->calc_rate(hw, &cfg, rate, *prate)) in clk_pll_round_rate()
866 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate() local
872 val = pll_readl_base(pll); in clk_pll_recalc_rate()
874 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) in clk_pll_recalc_rate()
877 if ((pll->params->flags & TEGRA_PLL_FIXED) && in clk_pll_recalc_rate()
878 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && in clk_pll_recalc_rate()
881 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, in clk_pll_recalc_rate()
887 return pll->params->fixed_rate; in clk_pll_recalc_rate()
890 _get_pll_mnp(pll, &cfg); in clk_pll_recalc_rate()
892 if (pll->params->flags & TEGRA_PLL_VCO_OUT) { in clk_pll_recalc_rate()
903 if (pll->params->set_gain) in clk_pll_recalc_rate()
904 pll->params->set_gain(&cfg); in clk_pll_recalc_rate()
914 static int clk_plle_training(struct tegra_clk_pll *pll) in clk_plle_training() argument
919 if (!pll->pmc) in clk_plle_training()
926 val = readl(pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
928 writel(val, pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
930 val = readl(pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
932 writel(val, pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
934 val = readl(pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
936 writel(val, pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
938 val = pll_readl_misc(pll); in clk_plle_training()
942 val = pll_readl_misc(pll); in clk_plle_training()
957 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_plle_enable() local
968 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_enable()
973 val = pll_readl_misc(pll); in clk_plle_enable()
975 pll_writel_misc(val, pll); in clk_plle_enable()
977 val = pll_readl_misc(pll); in clk_plle_enable()
979 err = clk_plle_training(pll); in clk_plle_enable()
984 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) { in clk_plle_enable()
986 val = pll_readl_base(pll); in clk_plle_enable()
987 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | in clk_plle_enable()
988 divm_mask_shifted(pll)); in clk_plle_enable()
990 val |= sel.m << divm_shift(pll); in clk_plle_enable()
991 val |= sel.n << divn_shift(pll); in clk_plle_enable()
992 val |= sel.p << divp_shift(pll); in clk_plle_enable()
994 pll_writel_base(val, pll); in clk_plle_enable()
997 val = pll_readl_misc(pll); in clk_plle_enable()
1000 pll_writel_misc(val, pll); in clk_plle_enable()
1002 val = readl(pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
1005 writel(val, pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
1007 val = pll_readl_base(pll); in clk_plle_enable()
1009 pll_writel_base(val, pll); in clk_plle_enable()
1011 clk_pll_wait_for_lock(pll); in clk_plle_enable()
1019 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_plle_recalc_rate() local
1020 u32 val = pll_readl_base(pll); in clk_plle_recalc_rate()
1024 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); in clk_plle_recalc_rate()
1025 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); in clk_plle_recalc_rate()
1026 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); in clk_plle_recalc_rate()
1036 struct tegra_clk_pll *pll = to_clk_pll(hw); in tegra_clk_pll_restore_context() local
1044 if (pll->params->set_defaults) in tegra_clk_pll_restore_context()
1045 pll->params->set_defaults(pll); in tegra_clk_pll_restore_context()
1078 /* UTMIP PLL Enable Delay Count */
1080 /* UTMIP PLL Stable count */
1082 /* UTMIP PLL Active delay count */
1084 /* UTMIP PLL Xtal frequency count */
1118 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pllu_enable() local
1134 if (pll->lock) in clk_pllu_enable()
1135 spin_lock_irqsave(pll->lock, flags); in clk_pllu_enable()
1140 ret = clk_pll_wait_for_lock(pll); in clk_pllu_enable()
1158 value = pll_readl_base(pll); in clk_pllu_enable()
1160 pll_writel_base(value, pll); in clk_pllu_enable()
1162 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_enable()
1163 /* Program UTMIP PLL stable and active counts */ in clk_pllu_enable()
1168 /* Remove power downs from UTMIP PLL control bits */ in clk_pllu_enable()
1172 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_enable()
1174 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()
1175 /* Program UTMIP PLL delay and oscillator frequency counts */ in clk_pllu_enable()
1180 /* Remove power downs from UTMIP PLL control bits */ in clk_pllu_enable()
1184 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()
1187 if (pll->lock) in clk_pllu_enable()
1188 spin_unlock_irqrestore(pll->lock, flags); in clk_pllu_enable()
1224 struct tegra_clk_pll *pll = to_clk_pll(hw); in _calc_dynamic_ramp_rate() local
1231 p = DIV_ROUND_UP(pll->params->vco_min, rate); in _calc_dynamic_ramp_rate()
1232 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate); in _calc_dynamic_ramp_rate()
1243 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max) in _calc_dynamic_ramp_rate()
1256 struct tegra_clk_pll *pll = to_clk_pll(hw); in tegra_pll_get_fixed_mdiv() local
1258 return (u16)_pll_fixed_mdiv(pll->params, input_rate); in tegra_pll_get_fixed_mdiv()
1307 struct tegra_clk_pll *pll = to_clk_pll(hw); in _pll_ramp_calc_pll() local
1314 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) { in _pll_ramp_calc_pll()
1321 if (cfg->p > pll->params->max_p) in _pll_ramp_calc_pll()
1331 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pllxc_set_rate() local
1340 if (pll->lock) in clk_pllxc_set_rate()
1341 spin_lock_irqsave(pll->lock, flags); in clk_pllxc_set_rate()
1343 _get_pll_mnp(pll, &old_cfg); in clk_pllxc_set_rate()
1344 if (pll->params->flags & TEGRA_PLL_VCO_OUT) in clk_pllxc_set_rate()
1350 if (pll->lock) in clk_pllxc_set_rate()
1351 spin_unlock_irqrestore(pll->lock, flags); in clk_pllxc_set_rate()
1359 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pll_ramp_round_rate() local
1372 if (pll->params->set_gain) in clk_pll_ramp_round_rate()
1373 pll->params->set_gain(&cfg); in clk_pll_ramp_round_rate()
1381 static void _pllcx_strobe(struct tegra_clk_pll *pll) in _pllcx_strobe() argument
1385 val = pll_readl_misc(pll); in _pllcx_strobe()
1387 pll_writel_misc(val, pll); in _pllcx_strobe()
1391 pll_writel_misc(val, pll); in _pllcx_strobe()
1396 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pllc_enable() local
1404 if (pll->lock) in clk_pllc_enable()
1405 spin_lock_irqsave(pll->lock, flags); in clk_pllc_enable()
1410 val = pll_readl_misc(pll); in clk_pllc_enable()
1412 pll_writel_misc(val, pll); in clk_pllc_enable()
1415 _pllcx_strobe(pll); in clk_pllc_enable()
1417 ret = clk_pll_wait_for_lock(pll); in clk_pllc_enable()
1419 if (pll->lock) in clk_pllc_enable()
1420 spin_unlock_irqrestore(pll->lock, flags); in clk_pllc_enable()
1427 struct tegra_clk_pll *pll = to_clk_pll(hw); in _clk_pllc_disable() local
1432 val = pll_readl_misc(pll); in _clk_pllc_disable()
1434 pll_writel_misc(val, pll); in _clk_pllc_disable()
1440 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pllc_disable() local
1443 if (pll->lock) in clk_pllc_disable()
1444 spin_lock_irqsave(pll->lock, flags); in clk_pllc_disable()
1448 if (pll->lock) in clk_pllc_disable()
1449 spin_unlock_irqrestore(pll->lock, flags); in clk_pllc_disable()
1452 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll, in _pllcx_update_dynamic_coef() argument
1477 val = pll_readl_misc(pll); in _pllcx_update_dynamic_coef()
1481 pll_writel_misc(val, pll); in _pllcx_update_dynamic_coef()
1490 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pllc_set_rate() local
1494 if (pll->lock) in clk_pllc_set_rate()
1495 spin_lock_irqsave(pll->lock, flags); in clk_pllc_set_rate()
1501 _get_pll_mnp(pll, &old_cfg); in clk_pllc_set_rate()
1515 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); in clk_pllc_set_rate()
1519 _update_pll_mnp(pll, &cfg); in clk_pllc_set_rate()
1525 if (pll->lock) in clk_pllc_set_rate()
1526 spin_unlock_irqrestore(pll->lock, flags); in clk_pllc_set_rate()
1531 static long _pllre_calc_rate(struct tegra_clk_pll *pll, in _pllre_calc_rate() argument
1538 m = _pll_fixed_mdiv(pll->params, parent_rate); in _pllre_calc_rate()
1556 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pllre_set_rate() local
1560 if (pll->lock) in clk_pllre_set_rate()
1561 spin_lock_irqsave(pll->lock, flags); in clk_pllre_set_rate()
1563 _pllre_calc_rate(pll, &cfg, rate, parent_rate); in clk_pllre_set_rate()
1564 _get_pll_mnp(pll, &old_cfg); in clk_pllre_set_rate()
1572 _update_pll_mnp(pll, &cfg); in clk_pllre_set_rate()
1576 ret = clk_pll_wait_for_lock(pll); in clk_pllre_set_rate()
1580 if (pll->lock) in clk_pllre_set_rate()
1581 spin_unlock_irqrestore(pll->lock, flags); in clk_pllre_set_rate()
1590 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pllre_recalc_rate() local
1593 _get_pll_mnp(pll, &cfg); in clk_pllre_recalc_rate()
1604 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pllre_round_rate() local
1606 return _pllre_calc_rate(pll, NULL, rate, *prate); in clk_pllre_round_rate()
1611 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_plle_tegra114_enable() local
1620 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_tegra114_enable()
1623 if (pll->lock) in clk_plle_tegra114_enable()
1624 spin_lock_irqsave(pll->lock, flags); in clk_plle_tegra114_enable()
1626 val = pll_readl_base(pll); in clk_plle_tegra114_enable()
1628 pll_writel_base(val, pll); in clk_plle_tegra114_enable()
1630 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1633 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1636 val = pll_readl_misc(pll); in clk_plle_tegra114_enable()
1642 pll_writel_misc(val, pll); in clk_plle_tegra114_enable()
1645 val = pll_readl(PLLE_SS_CTRL, pll); in clk_plle_tegra114_enable()
1647 pll_writel(val, PLLE_SS_CTRL, pll); in clk_plle_tegra114_enable()
1649 val = pll_readl_base(pll); in clk_plle_tegra114_enable()
1650 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | in clk_plle_tegra114_enable()
1651 divm_mask_shifted(pll)); in clk_plle_tegra114_enable()
1653 val |= sel.m << divm_shift(pll); in clk_plle_tegra114_enable()
1654 val |= sel.n << divn_shift(pll); in clk_plle_tegra114_enable()
1656 pll_writel_base(val, pll); in clk_plle_tegra114_enable()
1660 ret = clk_pll_wait_for_lock(pll); in clk_plle_tegra114_enable()
1665 val = pll_readl(PLLE_SS_CTRL, pll); in clk_plle_tegra114_enable()
1669 pll_writel(val, PLLE_SS_CTRL, pll); in clk_plle_tegra114_enable()
1671 pll_writel(val, PLLE_SS_CTRL, pll); in clk_plle_tegra114_enable()
1674 pll_writel(val, PLLE_SS_CTRL, pll); in clk_plle_tegra114_enable()
1677 /* Enable HW control of XUSB brick PLL */ in clk_plle_tegra114_enable()
1678 val = pll_readl_misc(pll); in clk_plle_tegra114_enable()
1680 pll_writel_misc(val, pll); in clk_plle_tegra114_enable()
1682 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1685 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1688 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1690 val = pll_readl(XUSBIO_PLL_CFG0, pll); in clk_plle_tegra114_enable()
1695 pll_writel(val, XUSBIO_PLL_CFG0, pll); in clk_plle_tegra114_enable()
1698 pll_writel(val, XUSBIO_PLL_CFG0, pll); in clk_plle_tegra114_enable()
1700 /* Enable HW control of SATA PLL */ in clk_plle_tegra114_enable()
1701 val = pll_readl(SATA_PLL_CFG0, pll); in clk_plle_tegra114_enable()
1705 pll_writel(val, SATA_PLL_CFG0, pll); in clk_plle_tegra114_enable()
1709 val = pll_readl(SATA_PLL_CFG0, pll); in clk_plle_tegra114_enable()
1711 pll_writel(val, SATA_PLL_CFG0, pll); in clk_plle_tegra114_enable()
1714 if (pll->lock) in clk_plle_tegra114_enable()
1715 spin_unlock_irqrestore(pll->lock, flags); in clk_plle_tegra114_enable()
1722 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_plle_tegra114_disable() local
1726 if (pll->lock) in clk_plle_tegra114_disable()
1727 spin_lock_irqsave(pll->lock, flags); in clk_plle_tegra114_disable()
1731 val = pll_readl_misc(pll); in clk_plle_tegra114_disable()
1733 pll_writel_misc(val, pll); in clk_plle_tegra114_disable()
1736 if (pll->lock) in clk_plle_tegra114_disable()
1737 spin_unlock_irqrestore(pll->lock, flags); in clk_plle_tegra114_disable()
1742 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_pllu_tegra114_enable() local
1757 if (pll->lock) in clk_pllu_tegra114_enable()
1758 spin_lock_irqsave(pll->lock, flags); in clk_pllu_tegra114_enable()
1763 ret = clk_pll_wait_for_lock(pll); in clk_pllu_tegra114_enable()
1781 value = pll_readl_base(pll); in clk_pllu_tegra114_enable()
1783 pll_writel_base(value, pll); in clk_pllu_tegra114_enable()
1785 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_tegra114_enable()
1786 /* Program UTMIP PLL stable and active counts */ in clk_pllu_tegra114_enable()
1791 /* Remove power downs from UTMIP PLL control bits */ in clk_pllu_tegra114_enable()
1795 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_tegra114_enable()
1797 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
1798 /* Program UTMIP PLL delay and oscillator frequency counts */ in clk_pllu_tegra114_enable()
1803 /* Remove power downs from UTMIP PLL control bits */ in clk_pllu_tegra114_enable()
1808 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
1811 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1815 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1817 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
1820 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
1828 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1831 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1836 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1838 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1841 if (pll->lock) in clk_pllu_tegra114_enable()
1842 spin_unlock_irqrestore(pll->lock, flags); in clk_pllu_tegra114_enable()
1847 static void _clk_plle_tegra_init_parent(struct tegra_clk_pll *pll) in _clk_plle_tegra_init_parent() argument
1852 val = pll_readl_base(pll); in _clk_plle_tegra_init_parent()
1853 val_aux = pll_readl(pll->params->aux_reg, pll); in _clk_plle_tegra_init_parent()
1863 pll_writel(val_aux, pll->params->aux_reg, pll); in _clk_plle_tegra_init_parent()
1864 fence_udelay(1, pll->clk_base); in _clk_plle_tegra_init_parent()
1873 struct tegra_clk_pll *pll; in _tegra_init_pll() local
1875 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in _tegra_init_pll()
1876 if (!pll) in _tegra_init_pll()
1879 pll->clk_base = clk_base; in _tegra_init_pll()
1880 pll->pmc = pmc; in _tegra_init_pll()
1882 pll->params = pll_params; in _tegra_init_pll()
1883 pll->lock = lock; in _tegra_init_pll()
1888 return pll; in _tegra_init_pll()
1891 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, in _tegra_clk_register_pll() argument
1904 if (!pll->params->calc_rate) { in _tegra_clk_register_pll()
1905 if (pll->params->flags & TEGRA_PLLM) in _tegra_clk_register_pll()
1906 pll->params->calc_rate = _calc_dynamic_ramp_rate; in _tegra_clk_register_pll()
1908 pll->params->calc_rate = _calc_rate; in _tegra_clk_register_pll()
1911 if (pll->params->set_defaults) in _tegra_clk_register_pll()
1912 pll->params->set_defaults(pll); in _tegra_clk_register_pll()
1915 pll->hw.init = &init; in _tegra_clk_register_pll()
1917 return tegra_clk_dev_register(&pll->hw); in _tegra_clk_register_pll()
1925 struct tegra_clk_pll *pll; in tegra_clk_register_pll() local
1930 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pll()
1931 if (IS_ERR(pll)) in tegra_clk_register_pll()
1932 return ERR_CAST(pll); in tegra_clk_register_pll()
1934 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pll()
1937 kfree(pll); in tegra_clk_register_pll()
1956 struct tegra_clk_pll *pll; in tegra_clk_register_plle() local
1964 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_plle()
1965 if (IS_ERR(pll)) in tegra_clk_register_plle()
1966 return ERR_CAST(pll); in tegra_clk_register_plle()
1968 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_plle()
1971 kfree(pll); in tegra_clk_register_plle()
1980 struct tegra_clk_pll *pll; in tegra_clk_register_pllu() local
1985 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllu()
1986 if (IS_ERR(pll)) in tegra_clk_register_pllu()
1987 return ERR_CAST(pll); in tegra_clk_register_pllu()
1989 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllu()
1992 kfree(pll); in tegra_clk_register_pllu()
2048 struct tegra_clk_pll *pll; in tegra_clk_register_pllxc() local
2072 * If the pll has a set_defaults callback, it will take care of in tegra_clk_register_pllxc()
2094 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllxc()
2095 if (IS_ERR(pll)) in tegra_clk_register_pllxc()
2096 return ERR_CAST(pll); in tegra_clk_register_pllxc()
2098 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllxc()
2101 kfree(pll); in tegra_clk_register_pllxc()
2113 struct tegra_clk_pll *pll; in tegra_clk_register_pllre() local
2122 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllre()
2123 if (IS_ERR(pll)) in tegra_clk_register_pllre()
2124 return ERR_CAST(pll); in tegra_clk_register_pllre()
2128 val = pll_readl_base(pll); in tegra_clk_register_pllre()
2136 val = m << divm_shift(pll); in tegra_clk_register_pllre()
2137 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); in tegra_clk_register_pllre()
2138 pll_writel_base(val, pll); in tegra_clk_register_pllre()
2143 val = pll_readl_misc(pll); in tegra_clk_register_pllre()
2145 pll_writel_misc(val, pll); in tegra_clk_register_pllre()
2147 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllre()
2150 kfree(pll); in tegra_clk_register_pllre()
2161 struct tegra_clk_pll *pll; in tegra_clk_register_pllm() local
2185 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllm()
2186 if (IS_ERR(pll)) in tegra_clk_register_pllm()
2187 return ERR_CAST(pll); in tegra_clk_register_pllm()
2189 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllm()
2192 kfree(pll); in tegra_clk_register_pllm()
2205 struct tegra_clk_pll *pll; in tegra_clk_register_pllc() local
2224 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllc()
2225 if (IS_ERR(pll)) in tegra_clk_register_pllc()
2226 return ERR_CAST(pll); in tegra_clk_register_pllc()
2230 * directly from PLL h/w. Hence, actual PLLC boot state is unknown. in tegra_clk_register_pllc()
2231 * Initialize PLL to default state: disabled, reset; shadow registers in tegra_clk_register_pllc()
2253 pll_writel_base(0, pll); in tegra_clk_register_pllc()
2254 _update_pll_mnp(pll, &cfg); in tegra_clk_register_pllc()
2256 pll_writel_misc(PLLCX_MISC_DEFAULT, pll); in tegra_clk_register_pllc()
2257 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); in tegra_clk_register_pllc()
2258 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); in tegra_clk_register_pllc()
2259 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); in tegra_clk_register_pllc()
2261 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); in tegra_clk_register_pllc()
2263 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllc()
2266 kfree(pll); in tegra_clk_register_pllc()
2277 struct tegra_clk_pll *pll; in tegra_clk_register_plle_tegra114() local
2280 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_plle_tegra114()
2281 if (IS_ERR(pll)) in tegra_clk_register_plle_tegra114()
2282 return ERR_CAST(pll); in tegra_clk_register_plle_tegra114()
2284 _clk_plle_tegra_init_parent(pll); in tegra_clk_register_plle_tegra114()
2286 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_plle_tegra114()
2289 kfree(pll); in tegra_clk_register_plle_tegra114()
2300 struct tegra_clk_pll *pll; in tegra_clk_register_pllu_tegra114() local
2305 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllu_tegra114()
2306 if (IS_ERR(pll)) in tegra_clk_register_pllu_tegra114()
2307 return ERR_CAST(pll); in tegra_clk_register_pllu_tegra114()
2309 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllu_tegra114()
2312 kfree(pll); in tegra_clk_register_pllu_tegra114()
2334 struct tegra_clk_pll *pll; in tegra_clk_register_pllss() local
2351 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllss()
2352 if (IS_ERR(pll)) in tegra_clk_register_pllss()
2353 return ERR_CAST(pll); in tegra_clk_register_pllss()
2355 val = pll_readl_base(pll); in tegra_clk_register_pllss()
2357 pll_writel_base(val, pll); in tegra_clk_register_pllss()
2363 /* initialize PLL to minimum rate */ in tegra_clk_register_pllss()
2371 kfree(pll); in tegra_clk_register_pllss()
2377 _update_pll_mnp(pll, &cfg); in tegra_clk_register_pllss()
2379 pll_writel_misc(PLLSS_MISC_DEFAULT, pll); in tegra_clk_register_pllss()
2380 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll); in tegra_clk_register_pllss()
2381 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll); in tegra_clk_register_pllss()
2382 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); in tegra_clk_register_pllss()
2384 val = pll_readl_base(pll); in tegra_clk_register_pllss()
2389 kfree(pll); in tegra_clk_register_pllss()
2398 pll_writel_base(val, pll); in tegra_clk_register_pllss()
2400 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllss()
2404 kfree(pll); in tegra_clk_register_pllss()
2417 struct tegra_clk_pll *pll; in tegra_clk_register_pllre_tegra210() local
2426 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllre_tegra210()
2427 if (IS_ERR(pll)) in tegra_clk_register_pllre_tegra210()
2428 return ERR_CAST(pll); in tegra_clk_register_pllre_tegra210()
2430 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllre_tegra210()
2433 kfree(pll); in tegra_clk_register_pllre_tegra210()
2440 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_plle_tegra210_is_enabled() local
2443 val = pll_readl_base(pll); in clk_plle_tegra210_is_enabled()
2450 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_plle_tegra210_enable() local
2462 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_tegra210_enable()
2465 if (pll->lock) in clk_plle_tegra210_enable()
2466 spin_lock_irqsave(pll->lock, flags); in clk_plle_tegra210_enable()
2468 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra210_enable()
2472 val = pll_readl_base(pll); in clk_plle_tegra210_enable()
2474 pll_writel_base(val, pll); in clk_plle_tegra210_enable()
2476 val = pll_readl_misc(pll); in clk_plle_tegra210_enable()
2482 pll_writel_misc(val, pll); in clk_plle_tegra210_enable()
2485 val = pll_readl(PLLE_SS_CTRL, pll); in clk_plle_tegra210_enable()
2487 pll_writel(val, PLLE_SS_CTRL, pll); in clk_plle_tegra210_enable()
2489 val = pll_readl_base(pll); in clk_plle_tegra210_enable()
2490 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | in clk_plle_tegra210_enable()
2491 divm_mask_shifted(pll)); in clk_plle_tegra210_enable()
2493 val |= sel.m << divm_shift(pll); in clk_plle_tegra210_enable()
2494 val |= sel.n << divn_shift(pll); in clk_plle_tegra210_enable()
2496 pll_writel_base(val, pll); in clk_plle_tegra210_enable()
2499 val = pll_readl_base(pll); in clk_plle_tegra210_enable()
2501 pll_writel_base(val, pll); in clk_plle_tegra210_enable()
2503 ret = clk_pll_wait_for_lock(pll); in clk_plle_tegra210_enable()
2508 val = pll_readl(PLLE_SS_CTRL, pll); in clk_plle_tegra210_enable()
2512 pll_writel(val, PLLE_SS_CTRL, pll); in clk_plle_tegra210_enable()
2514 pll_writel(val, PLLE_SS_CTRL, pll); in clk_plle_tegra210_enable()
2517 pll_writel(val, PLLE_SS_CTRL, pll); in clk_plle_tegra210_enable()
2521 if (pll->lock) in clk_plle_tegra210_enable()
2522 spin_unlock_irqrestore(pll->lock, flags); in clk_plle_tegra210_enable()
2529 struct tegra_clk_pll *pll = to_clk_pll(hw); in clk_plle_tegra210_disable() local
2533 if (pll->lock) in clk_plle_tegra210_disable()
2534 spin_lock_irqsave(pll->lock, flags); in clk_plle_tegra210_disable()
2537 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra210_disable()
2541 val = pll_readl_base(pll); in clk_plle_tegra210_disable()
2543 pll_writel_base(val, pll); in clk_plle_tegra210_disable()
2545 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra210_disable()
2547 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra210_disable()
2549 val = pll_readl_misc(pll); in clk_plle_tegra210_disable()
2551 pll_writel_misc(val, pll); in clk_plle_tegra210_disable()
2555 if (pll->lock) in clk_plle_tegra210_disable()
2556 spin_unlock_irqrestore(pll->lock, flags); in clk_plle_tegra210_disable()
2561 struct tegra_clk_pll *pll = to_clk_pll(hw); in tegra_clk_plle_t210_restore_context() local
2563 _clk_plle_tegra_init_parent(pll); in tegra_clk_plle_t210_restore_context()
2580 struct tegra_clk_pll *pll; in tegra_clk_register_plle_tegra210() local
2583 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_plle_tegra210()
2584 if (IS_ERR(pll)) in tegra_clk_register_plle_tegra210()
2585 return ERR_CAST(pll); in tegra_clk_register_plle_tegra210()
2587 _clk_plle_tegra_init_parent(pll); in tegra_clk_register_plle_tegra210()
2589 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_plle_tegra210()
2592 kfree(pll); in tegra_clk_register_plle_tegra210()
2605 struct tegra_clk_pll *pll; in tegra_clk_register_pllc_tegra210() local
2627 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllc_tegra210()
2628 if (IS_ERR(pll)) in tegra_clk_register_pllc_tegra210()
2629 return ERR_CAST(pll); in tegra_clk_register_pllc_tegra210()
2631 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllc_tegra210()
2634 kfree(pll); in tegra_clk_register_pllc_tegra210()
2645 struct tegra_clk_pll *pll; in tegra_clk_register_pllss_tegra210() local
2675 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllss_tegra210()
2676 if (IS_ERR(pll)) in tegra_clk_register_pllss_tegra210()
2677 return ERR_CAST(pll); in tegra_clk_register_pllss_tegra210()
2679 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllss_tegra210()
2683 kfree(pll); in tegra_clk_register_pllss_tegra210()
2694 struct tegra_clk_pll *pll; in tegra_clk_register_pllmb() local
2718 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllmb()
2719 if (IS_ERR(pll)) in tegra_clk_register_pllmb()
2720 return ERR_CAST(pll); in tegra_clk_register_pllmb()
2722 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllmb()
2725 kfree(pll); in tegra_clk_register_pllmb()