Lines Matching +full:din +full:- +full:ports
1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
232 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
233 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
234 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
235 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
237 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
238 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
239 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
240 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
241 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
242 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
244 #define mask(w) ((1 << (w)) - 1)
245 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
246 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
247 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
248 mask(p->params->div_nmp->divp_width))
249 #define sdm_din_mask(p) p->params->sdm_din_mask
250 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
252 #define divm_shift(p) (p)->params->div_nmp->divm_shift
253 #define divn_shift(p) (p)->params->div_nmp->divn_shift
254 #define divp_shift(p) (p)->params->div_nmp->divp_shift
264 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU)) argument
280 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) in clk_pll_enable_lock()
283 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) in clk_pll_enable_lock()
287 val |= BIT(pll->params->lock_enable_bit_idx); in clk_pll_enable_lock()
297 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { in clk_pll_wait_for_lock()
298 udelay(pll->params->lock_delay); in clk_pll_wait_for_lock()
302 lock_addr = pll->clk_base; in clk_pll_wait_for_lock()
303 if (pll->params->flags & TEGRA_PLL_LOCK_MISC) in clk_pll_wait_for_lock()
304 lock_addr += pll->params->misc_reg; in clk_pll_wait_for_lock()
306 lock_addr += pll->params->base_reg; in clk_pll_wait_for_lock()
308 lock_mask = pll->params->lock_mask; in clk_pll_wait_for_lock()
310 for (i = 0; i < pll->params->lock_delay; i++) { in clk_pll_wait_for_lock()
320 clk_hw_get_name(&pll->hw)); in clk_pll_wait_for_lock()
322 return -1; in clk_pll_wait_for_lock()
332 u32 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); in pllm_clk_is_gated_by_pmc()
345 * settings, including the enable-state. The PLLM is enabled when in clk_pll_is_enabled()
348 if ((pll->params->flags & TEGRA_PLLM) && pllm_clk_is_gated_by_pmc(pll)) in clk_pll_is_enabled()
361 if (pll->params->iddq_reg) { in _clk_pll_enable()
362 val = pll_readl(pll->params->iddq_reg, pll); in _clk_pll_enable()
363 val &= ~BIT(pll->params->iddq_bit_idx); in _clk_pll_enable()
364 pll_writel(val, pll->params->iddq_reg, pll); in _clk_pll_enable()
368 if (pll->params->reset_reg) { in _clk_pll_enable()
369 val = pll_readl(pll->params->reset_reg, pll); in _clk_pll_enable()
370 val &= ~BIT(pll->params->reset_bit_idx); in _clk_pll_enable()
371 pll_writel(val, pll->params->reset_reg, pll); in _clk_pll_enable()
377 if (pll->params->flags & TEGRA_PLL_BYPASS) in _clk_pll_enable()
382 if (pll->params->flags & TEGRA_PLLM) { in _clk_pll_enable()
383 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_enable()
385 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_enable()
395 if (pll->params->flags & TEGRA_PLL_BYPASS) in _clk_pll_disable()
400 if (pll->params->flags & TEGRA_PLLM) { in _clk_pll_disable()
401 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_disable()
403 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_disable()
406 if (pll->params->reset_reg) { in _clk_pll_disable()
407 val = pll_readl(pll->params->reset_reg, pll); in _clk_pll_disable()
408 val |= BIT(pll->params->reset_bit_idx); in _clk_pll_disable()
409 pll_writel(val, pll->params->reset_reg, pll); in _clk_pll_disable()
412 if (pll->params->iddq_reg) { in _clk_pll_disable()
413 val = pll_readl(pll->params->iddq_reg, pll); in _clk_pll_disable()
414 val |= BIT(pll->params->iddq_bit_idx); in _clk_pll_disable()
415 pll_writel(val, pll->params->iddq_reg, pll); in _clk_pll_disable()
422 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) { in pll_clk_start_ss()
423 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll); in pll_clk_start_ss()
425 val |= pll->params->ssc_ctrl_en_mask; in pll_clk_start_ss()
426 pll_writel(val, pll->params->ssc_ctrl_reg, pll); in pll_clk_start_ss()
432 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) { in pll_clk_stop_ss()
433 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll); in pll_clk_stop_ss()
435 val &= ~pll->params->ssc_ctrl_en_mask; in pll_clk_stop_ss()
436 pll_writel(val, pll->params->ssc_ctrl_reg, pll); in pll_clk_stop_ss()
449 if (pll->lock) in clk_pll_enable()
450 spin_lock_irqsave(pll->lock, flags); in clk_pll_enable()
458 if (pll->lock) in clk_pll_enable()
459 spin_unlock_irqrestore(pll->lock, flags); in clk_pll_enable()
469 if (pll->lock) in clk_pll_disable()
470 spin_lock_irqsave(pll->lock, flags); in clk_pll_disable()
476 if (pll->lock) in clk_pll_disable()
477 spin_unlock_irqrestore(pll->lock, flags); in clk_pll_disable()
483 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; in _p_div_to_hw()
486 while (p_tohw->pdiv) { in _p_div_to_hw()
487 if (p_div <= p_tohw->pdiv) in _p_div_to_hw()
488 return p_tohw->hw_val; in _p_div_to_hw()
491 return -EINVAL; in _p_div_to_hw()
493 return -EINVAL; in _p_div_to_hw()
498 return _p_div_to_hw(&pll->hw, p_div); in tegra_pll_p_div_to_hw()
504 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; in _hw_to_p_div()
507 while (p_tohw->pdiv) { in _hw_to_p_div()
508 if (p_div_hw == p_tohw->hw_val) in _hw_to_p_div()
509 return p_tohw->pdiv; in _hw_to_p_div()
512 return -EINVAL; in _hw_to_p_div()
526 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) in _get_table_rate()
527 if (sel->input_rate == parent_rate && in _get_table_rate()
528 sel->output_rate == rate) in _get_table_rate()
531 if (sel->input_rate == 0) in _get_table_rate()
532 return -EINVAL; in _get_table_rate()
534 if (pll->params->pdiv_tohw) { in _get_table_rate()
535 p = _p_div_to_hw(hw, sel->p); in _get_table_rate()
539 p = ilog2(sel->p); in _get_table_rate()
542 cfg->input_rate = sel->input_rate; in _get_table_rate()
543 cfg->output_rate = sel->output_rate; in _get_table_rate()
544 cfg->m = sel->m; in _get_table_rate()
545 cfg->n = sel->n; in _get_table_rate()
546 cfg->p = p; in _get_table_rate()
547 cfg->cpcon = sel->cpcon; in _get_table_rate()
548 cfg->sdm_data = sel->sdm_data; in _get_table_rate()
562 return -EINVAL; in _calc_rate()
590 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq; in _calc_rate()
591 cfg->output_rate <<= 1) in _calc_rate()
594 cfg->m = parent_rate / cfreq; in _calc_rate()
595 cfg->n = cfg->output_rate / cfreq; in _calc_rate()
596 cfg->cpcon = OUT_OF_TABLE_CPCON; in _calc_rate()
598 if (cfg->m == 0 || cfg->m > divm_max(pll) || in _calc_rate()
599 cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) || in _calc_rate()
600 cfg->output_rate > pll->params->vco_max) { in _calc_rate()
601 return -EINVAL; in _calc_rate()
604 cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m); in _calc_rate()
605 cfg->output_rate >>= p_div; in _calc_rate()
607 if (pll->params->pdiv_tohw) { in _calc_rate()
612 cfg->p = ret; in _calc_rate()
614 cfg->p = p_div; in _calc_rate()
620 * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
621 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
622 * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
634 if (!pll->params->sdm_din_reg) in clk_pll_set_sdm_data()
637 if (cfg->sdm_data) { in clk_pll_set_sdm_data()
639 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll); in clk_pll_set_sdm_data()
646 if (cfg->sdm_data == 0 && enabled) in clk_pll_set_sdm_data()
647 val &= ~pll->params->sdm_ctrl_en_mask; in clk_pll_set_sdm_data()
649 if (cfg->sdm_data != 0 && !enabled) in clk_pll_set_sdm_data()
650 val |= pll->params->sdm_ctrl_en_mask; in clk_pll_set_sdm_data()
659 struct tegra_clk_pll_params *params = pll->params; in _update_pll_mnp()
660 struct div_nmp *div_nmp = params->div_nmp; in _update_pll_mnp()
662 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && in _update_pll_mnp()
665 val = pll_override_readl(params->pmc_divp_reg, pll); in _update_pll_mnp()
666 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift); in _update_pll_mnp()
667 val |= cfg->p << div_nmp->override_divp_shift; in _update_pll_mnp()
668 pll_override_writel(val, params->pmc_divp_reg, pll); in _update_pll_mnp()
670 val = pll_override_readl(params->pmc_divnm_reg, pll); in _update_pll_mnp()
671 val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) | in _update_pll_mnp()
672 (divn_mask(pll) << div_nmp->override_divn_shift)); in _update_pll_mnp()
673 val |= (cfg->m << div_nmp->override_divm_shift) | in _update_pll_mnp()
674 (cfg->n << div_nmp->override_divn_shift); in _update_pll_mnp()
675 pll_override_writel(val, params->pmc_divnm_reg, pll); in _update_pll_mnp()
682 val |= (cfg->m << divm_shift(pll)) | in _update_pll_mnp()
683 (cfg->n << divn_shift(pll)) | in _update_pll_mnp()
684 (cfg->p << divp_shift(pll)); in _update_pll_mnp()
688 clk_pll_set_sdm_data(&pll->hw, cfg); in _update_pll_mnp()
696 struct tegra_clk_pll_params *params = pll->params; in _get_pll_mnp()
697 struct div_nmp *div_nmp = params->div_nmp; in _get_pll_mnp()
701 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && in _get_pll_mnp()
704 val = pll_override_readl(params->pmc_divp_reg, pll); in _get_pll_mnp()
705 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll); in _get_pll_mnp()
707 val = pll_override_readl(params->pmc_divnm_reg, pll); in _get_pll_mnp()
708 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll); in _get_pll_mnp()
709 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll); in _get_pll_mnp()
713 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll); in _get_pll_mnp()
714 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); in _get_pll_mnp()
715 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); in _get_pll_mnp()
717 if (pll->params->sdm_din_reg) { in _get_pll_mnp()
721 cfg->sdm_data = sdin_din_to_data(val); in _get_pll_mnp()
736 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT; in _update_pll_cpcon()
738 if (pll->params->flags & TEGRA_PLL_SET_LFCON) { in _update_pll_cpcon()
740 if (cfg->n >= PLLDU_LFCON_SET_DIVN) in _update_pll_cpcon()
742 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) { in _update_pll_cpcon()
744 if (rate >= (pll->params->vco_max >> 1)) in _update_pll_cpcon()
760 if (state && pll->params->pre_rate_change) { in _program_pll()
761 ret = pll->params->pre_rate_change(); in _program_pll()
768 if (state && pll->params->defaults_set && pll->params->dyn_ramp && in _program_pll()
769 (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) { in _program_pll()
770 ret = pll->params->dyn_ramp(pll, cfg); in _program_pll()
780 if (!pll->params->defaults_set && pll->params->set_defaults) in _program_pll()
781 pll->params->set_defaults(pll); in _program_pll()
785 if (pll->params->flags & TEGRA_PLL_HAS_CPCON) in _program_pll()
795 if (state && pll->params->post_rate_change) in _program_pll()
796 pll->params->post_rate_change(); in _program_pll()
809 if (pll->params->flags & TEGRA_PLL_FIXED) { in clk_pll_set_rate()
810 if (rate != pll->params->fixed_rate) { in clk_pll_set_rate()
813 pll->params->fixed_rate, rate); in clk_pll_set_rate()
814 return -EINVAL; in clk_pll_set_rate()
820 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) { in clk_pll_set_rate()
824 return -EINVAL; in clk_pll_set_rate()
826 if (pll->lock) in clk_pll_set_rate()
827 spin_lock_irqsave(pll->lock, flags); in clk_pll_set_rate()
830 if (pll->params->flags & TEGRA_PLL_VCO_OUT) in clk_pll_set_rate()
837 if (pll->lock) in clk_pll_set_rate()
838 spin_unlock_irqrestore(pll->lock, flags); in clk_pll_set_rate()
849 if (pll->params->flags & TEGRA_PLL_FIXED) { in clk_pll_round_rate()
851 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) in clk_pll_round_rate()
853 return pll->params->fixed_rate; in clk_pll_round_rate()
857 pll->params->calc_rate(hw, &cfg, rate, *prate)) in clk_pll_round_rate()
858 return -EINVAL; in clk_pll_round_rate()
874 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) in clk_pll_recalc_rate()
877 if ((pll->params->flags & TEGRA_PLL_FIXED) && in clk_pll_recalc_rate()
878 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && in clk_pll_recalc_rate()
881 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, in clk_pll_recalc_rate()
887 return pll->params->fixed_rate; in clk_pll_recalc_rate()
892 if (pll->params->flags & TEGRA_PLL_VCO_OUT) { in clk_pll_recalc_rate()
903 if (pll->params->set_gain) in clk_pll_recalc_rate()
904 pll->params->set_gain(&cfg); in clk_pll_recalc_rate()
919 if (!pll->pmc) in clk_plle_training()
920 return -ENOSYS; in clk_plle_training()
926 val = readl(pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
928 writel(val, pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
930 val = readl(pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
932 writel(val, pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
934 val = readl(pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
936 writel(val, pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
947 return -EBUSY; in clk_plle_training()
968 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_enable()
969 return -EINVAL; in clk_plle_enable()
984 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) { in clk_plle_enable()
1002 val = readl(pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
1005 writel(val, pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
1024 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); in clk_plle_recalc_rate()
1025 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); in clk_plle_recalc_rate()
1026 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); in clk_plle_recalc_rate()
1044 if (pll->params->set_defaults) in tegra_clk_pll_restore_context()
1045 pll->params->set_defaults(pll); in tegra_clk_pll_restore_context()
1049 if (!__clk_get_enable_count(hw->clk)) in tegra_clk_pll_restore_context()
1129 return -EINVAL; in clk_pllu_enable()
1134 if (pll->lock) in clk_pllu_enable()
1135 spin_lock_irqsave(pll->lock, flags); in clk_pllu_enable()
1154 ret = -EINVAL; in clk_pllu_enable()
1162 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_enable()
1165 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count); in clk_pllu_enable()
1167 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count); in clk_pllu_enable()
1172 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_enable()
1174 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()
1177 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count); in clk_pllu_enable()
1179 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count); in clk_pllu_enable()
1184 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()
1187 if (pll->lock) in clk_pllu_enable()
1188 spin_unlock_irqrestore(pll->lock, flags); in clk_pllu_enable()
1205 u16 mdiv = parent_rate / pll_params->cf_min; in _pll_fixed_mdiv()
1207 if (pll_params->flags & TEGRA_MDIV_NEW) in _pll_fixed_mdiv()
1208 return (!pll_params->mdiv_default ? mdiv : in _pll_fixed_mdiv()
1209 min(mdiv, pll_params->mdiv_default)); in _pll_fixed_mdiv()
1211 if (pll_params->mdiv_default) in _pll_fixed_mdiv()
1212 return pll_params->mdiv_default; in _pll_fixed_mdiv()
1214 if (parent_rate > pll_params->cf_max) in _pll_fixed_mdiv()
1229 return -EINVAL; in _calc_dynamic_ramp_rate()
1231 p = DIV_ROUND_UP(pll->params->vco_min, rate); in _calc_dynamic_ramp_rate()
1232 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate); in _calc_dynamic_ramp_rate()
1233 cfg->output_rate = rate * p; in _calc_dynamic_ramp_rate()
1234 cfg->n = cfg->output_rate * cfg->m / parent_rate; in _calc_dynamic_ramp_rate()
1235 cfg->input_rate = parent_rate; in _calc_dynamic_ramp_rate()
1241 cfg->p = p_div; in _calc_dynamic_ramp_rate()
1243 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max) in _calc_dynamic_ramp_rate()
1244 return -EINVAL; in _calc_dynamic_ramp_rate()
1258 return (u16)_pll_fixed_mdiv(pll->params, input_rate); in tegra_pll_get_fixed_mdiv()
1293 return -EINVAL; in _setup_dynamic_ramp()
1296 val = step_a << pll_params->stepa_shift; in _setup_dynamic_ramp()
1297 val |= step_b << pll_params->stepb_shift; in _setup_dynamic_ramp()
1298 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); in _setup_dynamic_ramp()
1314 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) { in _pll_ramp_calc_pll()
1316 err = -EINVAL; in _pll_ramp_calc_pll()
1321 if (cfg->p > pll->params->max_p) in _pll_ramp_calc_pll()
1322 err = -EINVAL; in _pll_ramp_calc_pll()
1340 if (pll->lock) in clk_pllxc_set_rate()
1341 spin_lock_irqsave(pll->lock, flags); in clk_pllxc_set_rate()
1344 if (pll->params->flags & TEGRA_PLL_VCO_OUT) in clk_pllxc_set_rate()
1350 if (pll->lock) in clk_pllxc_set_rate()
1351 spin_unlock_irqrestore(pll->lock, flags); in clk_pllxc_set_rate()
1372 if (pll->params->set_gain) in clk_pll_ramp_round_rate()
1373 pll->params->set_gain(&cfg); in clk_pll_ramp_round_rate()
1404 if (pll->lock) in clk_pllc_enable()
1405 spin_lock_irqsave(pll->lock, flags); in clk_pllc_enable()
1419 if (pll->lock) in clk_pllc_enable()
1420 spin_unlock_irqrestore(pll->lock, flags); in clk_pllc_enable()
1443 if (pll->lock) in clk_pllc_disable()
1444 spin_lock_irqsave(pll->lock, flags); in clk_pllc_disable()
1448 if (pll->lock) in clk_pllc_disable()
1449 spin_unlock_irqrestore(pll->lock, flags); in clk_pllc_disable()
1474 return -EINVAL; in _pllcx_update_dynamic_coef()
1494 if (pll->lock) in clk_pllc_set_rate()
1495 spin_lock_irqsave(pll->lock, flags); in clk_pllc_set_rate()
1525 if (pll->lock) in clk_pllc_set_rate()
1526 spin_unlock_irqrestore(pll->lock, flags); in clk_pllc_set_rate()
1538 m = _pll_fixed_mdiv(pll->params, parent_rate); in _pllre_calc_rate()
1545 cfg->m = m; in _pllre_calc_rate()
1546 cfg->n = n; in _pllre_calc_rate()
1560 if (pll->lock) in clk_pllre_set_rate()
1561 spin_lock_irqsave(pll->lock, flags); in clk_pllre_set_rate()
1580 if (pll->lock) in clk_pllre_set_rate()
1581 spin_unlock_irqrestore(pll->lock, flags); in clk_pllre_set_rate()
1620 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_tegra114_enable()
1621 return -EINVAL; in clk_plle_tegra114_enable()
1623 if (pll->lock) in clk_plle_tegra114_enable()
1624 spin_lock_irqsave(pll->lock, flags); in clk_plle_tegra114_enable()
1630 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1633 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1682 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1685 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1688 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1714 if (pll->lock) in clk_plle_tegra114_enable()
1715 spin_unlock_irqrestore(pll->lock, flags); in clk_plle_tegra114_enable()
1726 if (pll->lock) in clk_plle_tegra114_disable()
1727 spin_lock_irqsave(pll->lock, flags); in clk_plle_tegra114_disable()
1736 if (pll->lock) in clk_plle_tegra114_disable()
1737 spin_unlock_irqrestore(pll->lock, flags); in clk_plle_tegra114_disable()
1752 return -EINVAL; in clk_pllu_tegra114_enable()
1757 if (pll->lock) in clk_pllu_tegra114_enable()
1758 spin_lock_irqsave(pll->lock, flags); in clk_pllu_tegra114_enable()
1777 ret = -EINVAL; in clk_pllu_tegra114_enable()
1785 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_tegra114_enable()
1788 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count); in clk_pllu_tegra114_enable()
1790 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count); in clk_pllu_tegra114_enable()
1795 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_tegra114_enable()
1797 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
1800 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count); in clk_pllu_tegra114_enable()
1802 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count); in clk_pllu_tegra114_enable()
1808 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
1811 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1815 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1817 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
1820 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
1825 * Setup SW override of UTMIPLL assuming USB2.0 ports are assigned in clk_pllu_tegra114_enable()
1828 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1831 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1836 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1838 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1841 if (pll->lock) in clk_pllu_tegra114_enable()
1842 spin_unlock_irqrestore(pll->lock, flags); in clk_pllu_tegra114_enable()
1853 val_aux = pll_readl(pll->params->aux_reg, pll); in _clk_plle_tegra_init_parent()
1863 pll_writel(val_aux, pll->params->aux_reg, pll); in _clk_plle_tegra_init_parent()
1864 fence_udelay(1, pll->clk_base); in _clk_plle_tegra_init_parent()
1877 return ERR_PTR(-ENOMEM); in _tegra_init_pll()
1879 pll->clk_base = clk_base; in _tegra_init_pll()
1880 pll->pmc = pmc; in _tegra_init_pll()
1882 pll->params = pll_params; in _tegra_init_pll()
1883 pll->lock = lock; in _tegra_init_pll()
1885 if (!pll_params->div_nmp) in _tegra_init_pll()
1886 pll_params->div_nmp = &default_nmp; in _tegra_init_pll()
1904 if (!pll->params->calc_rate) { in _tegra_clk_register_pll()
1905 if (pll->params->flags & TEGRA_PLLM) in _tegra_clk_register_pll()
1906 pll->params->calc_rate = _calc_dynamic_ramp_rate; in _tegra_clk_register_pll()
1908 pll->params->calc_rate = _calc_rate; in _tegra_clk_register_pll()
1911 if (pll->params->set_defaults) in _tegra_clk_register_pll()
1912 pll->params->set_defaults(pll); in _tegra_clk_register_pll()
1915 pll->hw.init = &init; in _tegra_clk_register_pll()
1917 return tegra_clk_dev_register(&pll->hw); in _tegra_clk_register_pll()
1928 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pll()
1959 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_plle()
1961 if (!pll_params->div_nmp) in tegra_clk_register_plle()
1962 pll_params->div_nmp = &pll_e_nmp; in tegra_clk_register_plle()
1983 pll_params->flags |= TEGRA_PLLU; in tegra_clk_register_pllu()
2057 return ERR_PTR(-EINVAL); in tegra_clk_register_pllxc()
2060 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllxc()
2061 return ERR_PTR(-EINVAL); in tegra_clk_register_pllxc()
2065 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllxc()
2067 if (pll_params->adjust_vco) in tegra_clk_register_pllxc()
2068 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllxc()
2075 if (!pll_params->set_defaults) { in tegra_clk_register_pllxc()
2082 val = readl_relaxed(clk_base + pll_params->base_reg); in tegra_clk_register_pllxc()
2083 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); in tegra_clk_register_pllxc()
2086 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); in tegra_clk_register_pllxc()
2088 val_iddq |= BIT(pll_params->iddq_bit_idx); in tegra_clk_register_pllxc()
2090 clk_base + pll_params->iddq_reg); in tegra_clk_register_pllxc()
2116 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllre()
2118 if (pll_params->adjust_vco) in tegra_clk_register_pllre()
2119 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllre()
2130 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) & in tegra_clk_register_pllre()
2131 BIT(pll_params->iddq_bit_idx)); in tegra_clk_register_pllre()
2137 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); in tegra_clk_register_pllre()
2165 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllm()
2166 return ERR_PTR(-EINVAL); in tegra_clk_register_pllm()
2172 return ERR_PTR(-EINVAL); in tegra_clk_register_pllm()
2177 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllm()
2179 if (pll_params->adjust_vco) in tegra_clk_register_pllm()
2180 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllm()
2183 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllm()
2184 pll_params->flags |= TEGRA_PLLM; in tegra_clk_register_pllm()
2204 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; in tegra_clk_register_pllc()
2210 return ERR_PTR(-EINVAL); in tegra_clk_register_pllc()
2216 return ERR_PTR(-EINVAL); in tegra_clk_register_pllc()
2221 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllc()
2223 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllc()
2238 cfg.n = cfg.m * pll_params->vco_min / parent_rate; in tegra_clk_register_pllc()
2240 while (p_tohw->pdiv) { in tegra_clk_register_pllc()
2241 if (p_tohw->pdiv == 2) { in tegra_clk_register_pllc()
2242 cfg.p = p_tohw->hw_val; in tegra_clk_register_pllc()
2248 if (!p_tohw->pdiv) { in tegra_clk_register_pllc()
2250 return ERR_PTR(-EINVAL); in tegra_clk_register_pllc()
2257 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); in tegra_clk_register_pllc()
2258 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); in tegra_clk_register_pllc()
2259 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); in tegra_clk_register_pllc()
2303 pll_params->flags |= TEGRA_PLLU; in tegra_clk_register_pllu_tegra114()
2341 if (!pll_params->div_nmp) in tegra_clk_register_pllss()
2342 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss()
2348 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss()
2361 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllss()
2366 cfg.n = cfg.m * pll_params->vco_min / parent_rate; in tegra_clk_register_pllss()
2368 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++) in tegra_clk_register_pllss()
2372 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss()
2375 cfg.p = pll_params->pdiv_tohw[i-1].hw_val; in tegra_clk_register_pllss()
2380 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll); in tegra_clk_register_pllss()
2381 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll); in tegra_clk_register_pllss()
2382 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); in tegra_clk_register_pllss()
2385 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); in tegra_clk_register_pllss()
2387 if (val_iddq & BIT(pll_params->iddq_bit_idx)) { in tegra_clk_register_pllss()
2390 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss()
2393 val_iddq |= BIT(pll_params->iddq_bit_idx); in tegra_clk_register_pllss()
2394 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); in tegra_clk_register_pllss()
2420 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllre_tegra210()
2422 if (pll_params->adjust_vco) in tegra_clk_register_pllre_tegra210()
2423 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllre_tegra210()
2462 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_tegra210_enable()
2463 return -EINVAL; in clk_plle_tegra210_enable()
2465 if (pll->lock) in clk_plle_tegra210_enable()
2466 spin_lock_irqsave(pll->lock, flags); in clk_plle_tegra210_enable()
2468 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra210_enable()
2521 if (pll->lock) in clk_plle_tegra210_enable()
2522 spin_unlock_irqrestore(pll->lock, flags); in clk_plle_tegra210_enable()
2533 if (pll->lock) in clk_plle_tegra210_disable()
2534 spin_lock_irqsave(pll->lock, flags); in clk_plle_tegra210_disable()
2537 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra210_disable()
2545 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra210_disable()
2547 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra210_disable()
2555 if (pll->lock) in clk_plle_tegra210_disable()
2556 spin_unlock_irqrestore(pll->lock, flags); in clk_plle_tegra210_disable()
2604 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; in tegra_clk_register_pllc_tegra210()
2609 return ERR_PTR(-EINVAL); in tegra_clk_register_pllc_tegra210()
2615 return ERR_PTR(-EINVAL); in tegra_clk_register_pllc_tegra210()
2620 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllc_tegra210()
2622 if (pll_params->adjust_vco) in tegra_clk_register_pllc_tegra210()
2623 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllc_tegra210()
2626 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllc_tegra210()
2650 if (!pll_params->div_nmp) in tegra_clk_register_pllss_tegra210()
2651 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss_tegra210()
2657 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss_tegra210()
2660 val = readl_relaxed(clk_base + pll_params->base_reg); in tegra_clk_register_pllss_tegra210()
2663 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss_tegra210()
2668 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllss_tegra210()
2670 if (pll_params->adjust_vco) in tegra_clk_register_pllss_tegra210()
2671 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllss_tegra210()
2674 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllss_tegra210()
2698 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllmb()
2699 return ERR_PTR(-EINVAL); in tegra_clk_register_pllmb()
2705 return ERR_PTR(-EINVAL); in tegra_clk_register_pllmb()
2710 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllmb()
2712 if (pll_params->adjust_vco) in tegra_clk_register_pllmb()
2713 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllmb()
2716 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllmb()
2717 pll_params->flags |= TEGRA_PLLMB; in tegra_clk_register_pllmb()