1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
14 #define pll_out_override(p) (BIT((p->shift - 6)))
15 #define div_mask(d) ((1 << (d->width)) - 1)
16 #define get_mul(d) (1 << d->frac_width)
26 	div = div_frac_get(rate, parent_rate, divider->width,  in get_div()
27 			   divider->frac_width, divider->flags);  in get_div()
39 	u32 reg;  in clk_frac_div_recalc_rate()  local
43 	reg = readl_relaxed(divider->reg);  in clk_frac_div_recalc_rate()
45 	if ((divider->flags & TEGRA_DIVIDER_UART) &&  in clk_frac_div_recalc_rate()
46 	    !(reg & PERIPH_CLK_UART_DIV_ENB))  in clk_frac_div_recalc_rate()
49 	div = (reg >> divider->shift) & div_mask(divider);  in clk_frac_div_recalc_rate()
55 	rate += div - 1;  in clk_frac_div_recalc_rate()
92 	if (divider->lock)  in clk_frac_div_set_rate()
93 		spin_lock_irqsave(divider->lock, flags);  in clk_frac_div_set_rate()
95 	val = readl_relaxed(divider->reg);  in clk_frac_div_set_rate()
96 	val &= ~(div_mask(divider) << divider->shift);  in clk_frac_div_set_rate()
97 	val |= div << divider->shift;  in clk_frac_div_set_rate()
99 	if (divider->flags & TEGRA_DIVIDER_UART) {  in clk_frac_div_set_rate()
106 	if (divider->flags & TEGRA_DIVIDER_FIXED)  in clk_frac_div_set_rate()
109 	writel_relaxed(val, divider->reg);  in clk_frac_div_set_rate()
111 	if (divider->lock)  in clk_frac_div_set_rate()
112 		spin_unlock_irqrestore(divider->lock, flags);  in clk_frac_div_set_rate()
135 		const char *parent_name, void __iomem *reg,  in tegra_clk_register_divider()  argument
141 	struct clk_init_data init;  in tegra_clk_register_divider()  local
147 		return ERR_PTR(-ENOMEM);  in tegra_clk_register_divider()
150 	init.name = name;  in tegra_clk_register_divider()
151 	init.ops = &tegra_clk_frac_div_ops;  in tegra_clk_register_divider()
152 	init.flags = flags;  in tegra_clk_register_divider()
153 	init.parent_names = parent_name ? &parent_name : NULL;  in tegra_clk_register_divider()
154 	init.num_parents = parent_name ? 1 : 0;  in tegra_clk_register_divider()
156 	divider->reg = reg;  in tegra_clk_register_divider()
157 	divider->shift = shift;  in tegra_clk_register_divider()
158 	divider->width = width;  in tegra_clk_register_divider()
159 	divider->frac_width = frac_width;  in tegra_clk_register_divider()
160 	divider->lock = lock;  in tegra_clk_register_divider()
161 	divider->flags = clk_divider_flags;  in tegra_clk_register_divider()
163 	/* Data in .init is copied by clk_register(), so stack variable OK */  in tegra_clk_register_divider()
164 	divider->hw.init = &init;  in tegra_clk_register_divider()
166 	clk = clk_register(NULL, &divider->hw);  in tegra_clk_register_divider()
180 				  void __iomem *reg, spinlock_t *lock)  in tegra_clk_register_mc()  argument
184 					  reg, 16, 1, CLK_DIVIDER_READ_ONLY,  in tegra_clk_register_mc()